Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: Semiconductor structures and method for manufacturing the same are provided. The semiconductor structure includes a substrate and a first fin structure formed over the substrate. The semiconductor structure also includes an isolation structure formed around the first fin structure and a protection layer formed on the isolation structure. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure surrounding the first nanostructures. In addition, a bottom surface of the gate structure and the top surface of the isolation structure are separated by the protection layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.

Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A waterproof click pad device includes a click pad, a frame and a waterproof unit. The frame surrounds the click pad and surrounds an axis passing through the click pad. The waterproof unit is transverse to the axis and is in sheet form. The waterproof unit includes a frame adhesive member surrounding the axis and adhered to the frame, a first non-adhesive member surrounding the axis, connected to an inner periphery of the frame adhesive member and spaced apart from and located above the frame, a second non-adhesive member surrounding the axis, connected to an inner periphery of the first non-adhesive member and spaced apart from and located above the click pad and the frame, and an plate adhesive member connected to an inner periphery of the second non-adhesive member and adhered to the click pad.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.

Abstract: A composite optical film comprises a first optical film and a second optical film disposed on the first optical film, wherein the first optical film comprises a first substrate; a plurality of reversed prisms disposed on a bottom surface of the first substrate; and a first diffusion film disposed over a top surface of the first substrate; and the second optical film comprises a first PET film thereon having a first set of prisms and a second PET film having a second set of prisms thereon, wherein the first PET film and the second PET film are laminated together.

Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.

Abstract: Semiconductor structures and method for manufacturing the same are provided. The semiconductor structure includes a substrate and a first fin structure formed over the substrate. The semiconductor structure also includes an isolation structure formed around the first fin structure and a protection layer formed on the isolation structure. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure surrounding the first nanostructures. In addition, a bottom surface of the gate structure and the top surface of the isolation structure are separated by the protection layer.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.

Abstract: A resonant energy stabilizer contains: a body, a lid, a mineral crystal, the current amplifier, and a medium frequency current device. The body includes an accommodation chamber. The lid includes an accommodating room. The mineral crystal includes a recess configured to accommodate a sapphire for producing far-infrared waves of electrostatic pulse. The recess is surrounded by a white crystal, a citrine and a green crystal which are surrounded by multiple titanium crystals, and a first magnetite is located above the white crystal, the citrine and the green crystal. The current amplifier includes multiple plasma pieces stacked together to increase a distance of the far-infrared waves of the electrostatic pulse, and each plasma piece has a copper coil layer, a red brass patch, and a red copper sheet. The medium frequency current device includes multiple second magnetites, an input segment, a central processing unit, a booster, and an output segment.

Abstract: A resonant energy stabilizer contains: a body, a lid, a mineral crystal, the current amplifier, and a medium frequency current device. The body includes an accommodation chamber. The lid includes an accommodating room. The mineral crystal includes a recess configured to accommodate a sapphire for producing far-infrared waves of electrostatic pulse. The recess is surrounded by a white crystal, a citrine and a green crystal which are surrounded by multiple titanium crystals, and a first magnetite is located above the white crystal, the citrine and the green crystal. The current amplifier includes multiple plasma pieces stacked together to increase a distance of the far-infrared waves of the electrostatic pulse, and each plasma piece has a copper coil layer, a red brass patch, and a red copper sheet. The medium frequency current device includes multiple second magnetites, an input segment, a central processing unit, a booster, and an output segment.

Abstract: A keyswitch device includes a base plate, a membrane circuit board, a light source, and a keyswitch assembly. The membrane circuit board is disposed on the base plate and includes a reflective film layer, a transmissive film layer, and a light guide spacer. The reflective film layer is located on the base plate. The transmissive film layer is located over the reflective film layer. The light guide spacer has an accommodating space. The reflective film layer and the transmissive film layer are respectively located at opposite sides of the light guide spacer. The light source is disposed between the reflective film layer and the transmissive film layer and located in the accommodating space. The keyswitch assembly is disposed on the membrane circuit board.

Abstract: A keyswitch device includes a base plate, a membrane circuit board, a light source, and a keyswitch assembly. The membrane circuit board is disposed on the base plate and includes a reflective film layer, a transmissive film layer, and a light guide spacer. The reflective film layer is located on the base plate. The transmissive film layer is located over the reflective film layer. The light guide spacer has an accommodating space. The reflective film layer and the transmissive film layer are respectively located at opposite sides of the light guide spacer. The light source is disposed between the reflective film layer and the transmissive film layer and located in the accommodating space. The keyswitch assembly is disposed on the membrane circuit board.

Abstract: A light-emitting keyboard includes a membrane circuit board including a lower layer, an upper layer and a light-guiding spacer layer arranged between lower layer, an upper layer and defining therein a tapered through hole, a substrate holding membrane circuit board, a key assembly including key cap, a linkage coupled between key cap and substrate and an elastic element supported between key cap and membrane circuit board, and a light source for emitting light into the light-guiding spacer layer. The light-guiding spacer layer uses its thickness to isolate the lower layer and the upper layer and its tapered through hole to provide room for a triggering stroke for enabling the upper layer to electrically contact the lower layer second circuit in producing a corresponding switching signal each time the key assembly is pressed. Thus, the light-emitting keyboard achieves the characteristics of low profile, low manufacturing cost, and simple assembly process.