Patents by Inventor Ching-Chiang Wu
Ching-Chiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230093515Abstract: A synchronous buck converter using a single gate drive control is provided and includes a drive circuit, a p-type gallium nitride (p-GaN) transistor switch module and an inductor. A gallium nitride power transistor is used as an upper side transistor switch, and a PMOS power transistor is used as a lower side transistor switch in the p-GaN transistor switch module. A gate of the upper side transistor switch and a gate of the lower side transistor switch are coupled to each other and receive a switch signal provided by the drive circuit at the same time. By controlling the on and off of the upper side transistor switch and the lower side transistor switch, the problem of simultaneous activation of the upper and lower side transistor switches can be avoided.Type: ApplicationFiled: December 1, 2021Publication date: March 23, 2023Inventors: Wei-Hua Chieng, Edward Yi Chang, Stone Cheng, Shyr-Long Jeng, Li-Chuan Tang, Chih-Chiang Wu, Ching-Yao Liu, Kuo-Bin Wang
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Patent number: 11574857Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.Type: GrantFiled: March 23, 2020Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Chien-Chang Lin
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Publication number: 20230029820Abstract: An image sensor is provided. The image sensor includes a substrate, an isolation structure on the substrate, a photoelectric conversion layer, a transparent electrode layer, an encapsulation layer, a color filter layer, and a micro-lens. The isolation structure is electrically non-conductive and defines a plurality of pixel regions on the substrate. The isolation structure prevents cross-talk of electrical signals among pixels. The photoelectric conversion layer is disposed on the pixel regions defined by the isolation structure. The transparent electrode layer is disposed over the isolation structure and the photoelectric conversion layer. The encapsulation layer is disposed over the transparent electrode layer. The micro-lens is disposed on the color filter layer.Type: ApplicationFiled: August 2, 2021Publication date: February 2, 2023Inventors: Wei-Lung TSAI, Shin-Hong KUO, Huang-Jen CHEN, Yu-Chi CHANG, Ching-Chiang WU, Han-Lin WU, Hung-Jen TSAI
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Patent number: 11569696Abstract: A control method of a minimum power input applicable to a wireless power transfer system including a power transmission unit and at least one power receiving unit is provided. The power transmission unit is electrically connected with a control voltage signal and an input voltage signal and accordingly generates the minimum power input. The power transmission unit transmits the minimum power input wirelessly through a wireless transmission to the at least one power receiving unit for receiving. By adjusting the input voltage signal, the duty ratio and resonant frequency of the control voltage signal, the present invention ensures an optimal power transmission efficiency of the wireless power transmission system. Moreover, parameters of a charge pump reservoir and gate driving circuit can be further designed in view of the trend feedback of its gate drive waveforms so as to optimize the effect of the proposed invention.Type: GrantFiled: May 28, 2021Date of Patent: January 31, 2023Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Wei-Hua Chieng, Edward Yi Chang, Stone Cheng, Shyr-Long Jeng, Newton Tang, Chih-Chiang Wu, Ching-Yao Liu, Kuo-Bin Wang
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Publication number: 20230020741Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements. The solid-state image sensor also includes a mosaic pattern layer disposed above the photoelectric conversion elements. The mosaic pattern layer includes an infrared-passing segment and color filter segments disposed on the periphery of the infrared-passing segment. The solid-state image sensor further includes a first condensing structure disposed on the mosaic pattern layer. The infrared-passing segment and the color filter segments share the first condensing structure.Type: ApplicationFiled: July 19, 2021Publication date: January 19, 2023Inventors: Hao-Wei LIU, Chia-Chien HSIEH, Sheng-Chuan CHENG, Ching-Chiang WU
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Publication number: 20220382069Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, and wherein the conductive layer is formed over at least one of the following: the first surface of the first dielectric layer and a portion of sidewalls of each of the plurality of via holes, and wherein the conductive layer is configured so as to allow the optical collimator to filter light in a range of wavelengths.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: Hsin-Yu CHEN, Yen-Chiang Liu, Jiun-Jie Chiou, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Hsi-Cheng Hsu
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Publication number: 20220320024Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
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Patent number: 11454820Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction.Type: GrantFiled: October 17, 2019Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yu Chen, Yen-Chiang Liu, Jiun-Jie Chiou, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Hsi-Cheng Hsu
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Publication number: 20220302182Abstract: An optical device is provided. The optical device includes a substrate and a plurality of optical structures. The substrate includes a plurality of photoelectric conversion elements. The optical structures are disposed above the substrate. Each optical structure corresponds to one photoelectric conversion element. Each optical structure includes a first portion and a second portion. The first portion has a first glass transition temperature. The second portion has a second glass transition temperature. The second portion guides the incident light into the photoelectric conversion element. The first glass transition temperature is higher than the second glass transition temperature.Type: ApplicationFiled: December 28, 2021Publication date: September 22, 2022Inventors: Shin-Hong KUO, Han-Lin WU, Ta-Yung NI, Ching-Chiang WU, Zong-Ru TU, Yu-Chi CHANG, Hung-Jen TSAI
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Publication number: 20220285999Abstract: A control method of a minimum power input applicable to a wireless power transfer system including a power transmission unit and at least one power receiving unit is provided. The power transmission unit is electrically connected with a control voltage signal and an input voltage signal and accordingly generates the minimum power input. The power transmission unit transmits the minimum power input wirelessly through a wireless transmission to the at least one power receiving unit for receiving. By adjusting the input voltage signal, the duty ratio and resonant frequency of the control voltage signal, the present invention ensures an optimal power transmission efficiency of the wireless power transmission system. Moreover, parameters of a charge pump reservoir and gate driving circuit can be further designed in view of the trend feedback of its gate drive waveforms so as to optimize the effect of the proposed invention.Type: ApplicationFiled: May 28, 2021Publication date: September 8, 2022Applicant: National Yang Ming Chiao Tung UniversityInventors: Wei-Hua Chieng, Edward Yi Chang, Stone Cheng, Shyr-Long Jeng, Newton Tang, Chih-Chiang Wu, Ching-Yao Liu, Kuo-Bin Wang
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Publication number: 20220285241Abstract: A method of forming a semiconductor package includes the following steps. A redistribution layer structure is formed over a first die and a dummy die, wherein the redistribution layer structure is directly electrically connected to the first die. An insulating layer is formed, wherein the insulating layer is disposed opposite to the redistribution layer structure with respect to the first die. At least one thermal through via is formed in the insulating layer.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Yi-Che Chiang
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Publication number: 20220262685Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
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Patent number: 11398440Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.Type: GrantFiled: October 22, 2018Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
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Publication number: 20220231074Abstract: An image sensor is provided. The image sensor includes a substrate, first photodiodes, second photodiodes, an interlayer, a light-guiding structure, and a micro-lens layer. The first photodiodes and the second photodiodes are alternately disposed in the substrate. The area of each of the first photodiodes is less than the area of each of the second photodiodes from a top view. The interlayer is disposed on the substrate. The light-guiding structure is disposed in the interlayer and over at least one of the first photodiodes or the second photodiodes. The refractive index of the light-guiding structure is greater than the refractive index of the interlayer. The micro-lens layer is disposed on the interlayer.Type: ApplicationFiled: January 19, 2021Publication date: July 21, 2022Inventors: Yuan-Shuo CHANG, Ching-Chiang WU
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Patent number: 11387824Abstract: A voltage-controlled varied frequency pulse width modulator is provided, including a frequency-regulating voltage output device which receives a determining voltage, decides a resonant frequency according to the determining voltage and outputs an oscillation signal having the resonant frequency. A duty-ratio-regulating voltage output device receives the oscillation signal and a reference signal to determine a duty ratio through an inverting closed loop, so as to adjust the oscillation signal to have the duty ratio. By employing the proposed voltage-controlled modulator circuit with tunable frequency and varied pulse width of the present invention, a modulation signal having the determined resonant frequency and duty ratio is obtained. Moreover, the present invention can be further combined with gate drive waveform trend feedback designs to achieve superior power transmission efficiency of a wireless power transmission system to optimize the inventive effect of the present invention.Type: GrantFiled: October 29, 2021Date of Patent: July 12, 2022Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Wei-Hua Chieng, Edward Yi Chang, Stone Cheng, Shyr-Long Jeng, Li-Chuan Tang, Chih-Chiang Wu, Yueh-Tsung Hsieh, Ching-Yao Liu, Kuo-Bin Wang
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Publication number: 20220216201Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11373922Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.Type: GrantFiled: August 14, 2020Date of Patent: June 28, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Yi-Che Chiang
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Patent number: 10770496Abstract: An optical sensor includes an optical layer disposed on a substrate, and a light shielding layer disposed on the optical layer, wherein the light shielding layer includes a first opening that partially exposes the optical layer. The optical sensor also includes a polymer material layer that fills the first opening, wherein a top surface of the polymer material layer is higher than a top surface of the light shielding layer. The optical sensor further includes an adhesive layer disposed on the light shielding layer and the polymer material layer, and a surface component disposed on the adhesive layer.Type: GrantFiled: April 16, 2018Date of Patent: September 8, 2020Assignee: VISERA TECHNOLOGIES COMPANY LIMITEDInventors: Ching-Chiang Wu, Ho-Tai Lin, Masafumi Sano
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Publication number: 20190319059Abstract: An optical sensor includes an optical layer disposed on a substrate, and a light shielding layer disposed on the optical layer, wherein the light shielding layer includes a first opening that partially exposes the optical layer. The optical sensor also includes a polymer material layer that fills the first opening, wherein a top surface of the polymer material layer is higher than a top surface of the light shielding layer. The optical sensor further includes an adhesive layer disposed on the light shielding layer and the polymer material layer, and a surface component disposed on the adhesive layer.Type: ApplicationFiled: April 16, 2018Publication date: October 17, 2019Inventors: Ching-Chiang WU, Ho-Tai LIN, Masafumi SANO
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Patent number: 7122458Abstract: A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over the seed layer to expose a portion thereof over the bonding pad, and a metal layer is then formed thereon. A sacrificial layer is then formed over the substrate and the sacrificial layer over the patterned mask layer is removed. The conductive film exposed by the metal layer and the remaining sacrificial layer is then removed, leaving a pad redistribution layer for the bonding pad.Type: GrantFiled: July 22, 2004Date of Patent: October 17, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Jen Cheng, Hui-Mei Yu, Li-Hsin Tseng, Tzu-Han Lin, Ching-Chiang Wu, Chun-Yen Lo, Li-Chuan Huang, Boe Su