Patents by Inventor Ching-Chieh Lin

Ching-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200081641
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Application
    Filed: November 17, 2019
    Publication date: March 12, 2020
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Publication number: 20200066831
    Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
    Type: Application
    Filed: September 30, 2019
    Publication date: February 27, 2020
    Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
  • Patent number: 10573736
    Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: February 25, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang, Wen-Chia Liao, Ching-Chuan Shiue, Shih-Peng Chen
  • Publication number: 20200058627
    Abstract: A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
  • Patent number: 10553747
    Abstract: A semiconductor device comprises a substrate, a first semiconductor unit on the substrate, and an first adhesion structure between the substrate and the first semiconductor unit, and directly contacting the first semiconductor unit and the substrate, wherein the first adhesion structure comprises an adhesion layer and a sacrificial layer, and the adhesion layer and the sacrificial layer are made of different materials, and wherein an adhesion between the first semiconductor unit and the adhesion layer is different from that between the first semiconductor unit and the sacrificial layer.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 4, 2020
    Assignee: Epistar Corporation
    Inventors: Chih-Chiang Lu, Yi-Ming Chen, Chun-Yu Lin, Ching-Pei Lin, Chung-Hsun Chien, Chien-Fu Huang, Hao-Min Ku, Min-Hsun Hsieh, Tzu-Chieh Hsu
  • Patent number: 10544261
    Abstract: The present invention relates to a phosphinated poly(2,6-dimethy phenylene oxide)oligomer, specifically an unsaturated group-containing phosphinated poly(2,6-dimethy phenylene oxide)oligomer, and processes for producing the same. A thermoset produced from the unsaturated group-containing phosphinated poly(2,6-dimethy phenylene oxide)oligomers according to the present invention exhibits flame retardancy and has a low dielectric constant and dissipation factor and a high glass transition temperature.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: January 28, 2020
    Assignee: Chang Chun Plastics Co., Ltd.
    Inventors: Ching Hsuan Lin, Ping-Chieh Wang, An-Pang Tu, Kuen-Yuan Hwang, Chun Yu Tseng
  • Publication number: 20200020791
    Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Li-Fan LIN, Chun-Chieh YANG, Wen-Chia LIAO, Ching-Chuan SHIUE, Shih-Peng CHEN
  • Publication number: 20200013235
    Abstract: A method and an apparatus for processing patches of a point cloud are provided. The apparatus includes an input/output (I/O) device, a storage device, and a processor. The I/O device is used to receive a bit stream of the point cloud. The storage device is configured to store an index table recording indexes corresponding to a plurality of orientations. The processor is coupled to the I/O device and the storage device and is configured to execute a program to demultiplex the bit stream of the point cloud into a patch image and indexes corresponding to a plurality of patches in the patch image, look up the index table obtain an orientation of each patch, transform the patch image according to the orientation to recover the plurality of patches of the point cloud, and reconstruct the point cloud by using the recovered patches.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 9, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Yi-Ting Tsai, Chun-Lung Lin, Ching-Chieh Lin
  • Publication number: 20200007872
    Abstract: A video decoding method includes: receiving a coding value; and performing the following steps according to an index value of the coding value: collecting a plurality of reference samples, grouping the plurality of reference samples to generate at least one group, establishing a model of the at least one group, obtaining a target pixel from a target block, selecting a target group from the at least one group, and introducing a luminance value of the target pixel into a model of the target group to predict a chromaticity value of the target pixel.
    Type: Application
    Filed: June 19, 2019
    Publication date: January 2, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Po WANG, Chun-Lung LIN, Ching-Chieh LIN, Chang-Hao YAU, Po-Han LIN
  • Publication number: 20200007862
    Abstract: A method of adaptive filtering for multiple reference line of intra prediction in video coding, a video encoding apparatus and video decoding apparatus therewith are provided in the disclosure. In the method of intra prediction in video coding, a method of adaptive filtering is used to dynamically determine operation of filtering is applied to input samples in the intra prediction or not, which can reduce the complexity of the intra prediction in video coding if multiple reference lines are used for the operation of the intra prediction, and also increase the efficiency of compressing performance of ultra-high resolution video.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 2, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Ching-Chieh Lin, Chun-Lung Lin
  • Patent number: 10521142
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: December 31, 2019
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Publication number: 20190388230
    Abstract: An artificial joint includes a first joint assembly and a second joint assembly. The first joint assembly is adapted to be connected to a first bone and has a first contacting surface, wherein the first contacting surface includes a first convex arc surface, a second convex arc surface, and a third convex arc surface. The second joint assembly is adapted to be connected to a second bone and has a second contacting surface, wherein the second contacting surface is in contact with the first contacting surface and includes a first concave arc surface, a second concave arc surface, and a third concave arc surface, and the first concave arc surface, the second concave arc surface, and the third concave arc surface respectively correspond to the first convex arc surface, the second convex arc surface, and the third convex arc surface.
    Type: Application
    Filed: December 19, 2018
    Publication date: December 26, 2019
    Applicants: Industrial Technology Research Institute, National Taiwan University Hospital
    Inventors: Pei-I Tsai, Hsin-Hsin Shen, Kuo-Yi Yang, De-Yau Lin, Yi-Hung Wen, Chih-Chieh Huang, Wei-Luan Fan, Pei-Yu Chen, Ching-Chi Hsu
  • Patent number: 10507041
    Abstract: A bionic fixing apparatus is provided. The bionic fixing apparatus includes a body having a through hole and at least one slit. The through hole penetrates the body from the top surface to the bottom surface to form a top opening and a bottom opening. An inner diameter of the top opening is larger than an inner diameter of the bottom opening. The slit is connected to the bottom opening and extends upwardly from the bottom surface of the body, such that the body has a flexible bottom portion.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 17, 2019
    Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL TAIWAN UNIVERSITY HOSPITAL
    Inventors: Pei-Yi Tsai, Chih-Chieh Huang, Yi-Hung Wen, Hsin-Hsin Shen, Yi-Hung Lin, De-Yau Lin, Jui-Sheng Sun, Chuan-Sheng Chuang, An-Li Chen, Ching-Chih Lin
  • Publication number: 20190363126
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 28, 2019
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20190348564
    Abstract: A photodetector is provided with a metal-semiconductor junction for measuring infrared radiation. In another embodiment, the photodetector includes structures to achieve localized surface plasmon resonance at the metal-semiconductor junction stimulated by incident light. The photodetector hence has prompted response and broadband spectra region for photon detection. The photodetector can be used for detecting varied powers of incident light with wavelength from visible to mid-infrared region (300 nm˜20 ?m).
    Type: Application
    Filed: March 6, 2019
    Publication date: November 14, 2019
    Inventors: Ching-Fuh Lin, Hung-Chieh Chuang, Meng-Jie Lin, Po-Jui Huang
  • Patent number: 10475877
    Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
  • Publication number: 20190340330
    Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan WU, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
  • Patent number: 10468516
    Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 5, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang, Wen-Chia Liao, Ching-Chuan Shiue, Shih-Peng Chen
  • Patent number: 10414088
    Abstract: A platform structure for manufacturing a scaffold for use in tissue engineering, comprising a frame; a ring-shaped thermally conductive member fixedly disposed in the frame; a thermally conductive platform centrally movably disposed in the ring-shaped thermally conductive member and having edges in direct contact with inner walls of the ring-shaped thermally conductive member, wherein the thermally conductive platform and the ring-shaped thermally conductive member together define a space of a variable depth; a vertically movable mechanism connected to a bottom of the thermally conductive platform and adapted to drive the thermally conductive platform to sink and thus increase gradually the depth of the space; and a low temperature generating mechanism connected to the ring-shaped thermally conductive member and the thermally conductive platform to cool down the ring-shaped thermally conductive member and the thermally conductive platform, to prevent deformation and ensure uniform dimensions of tall scaffolds
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 17, 2019
    Assignee: NATIONAL CENTRAL UNIVERSITY
    Inventors: Chao-Yaug Liao, Ching-Shiow Tseng, Fang-Chieh Tu, Yen-Sheng Lin, Wei-Jen Wu
  • Publication number: 20190259906
    Abstract: A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 22, 2019
    Inventors: Hsin-Chih Chiu, Chih-Chiang Lu, Chun-Yu Lin, Ching-Huai Ni, Yi-Ming Chen, Tzu-Chieh Hsu, Ching-Pei Lin