Abstract: A controller for filtering sub-channels of DVB is provided, including a media access control (MAC) unit, at least a data compression unit and at least a physical interface circuit. The MAC unit includes a plurality of registers. The MAC unit is connected to the DVB packets through a bus, and the registers provide storage for the program identification of at least one DVB sub-channel packet so that the MAC unit can determine whether to discard or output the DVB packet based on the program identification. The data compression unit is connected to MAC unit for being controlled to determine whether the packet should be compressed before output. The physical interface circuit is connected to the MAC unit and the data compression unit for outputting the compressed or uncompressed packets.

Abstract: An automatic feedback adjustment device for a digital antenna includes a digital antenna unit, a trafficator, a tuner, a demodulator, an antenna direction driver unit, a secondary controller, and a primary controller. The digital antenna unit is a digital video/broadcasting antenna system. The trafficator is connected to the digital antenna unit to retrieve direction data associated with the actual elevation angle and direction. The tuner is connected to the digital antenna unit and the demodulator is connected to the tuner in order to receive and convert a transmission signal from a transmission terminal into the video data and a received-signal quality signal. The antenna direction driver unit is connected to the digital antenna unit in order to drive adjustment of direction and elevation angle of the antenna.

Abstract: A storage apparatus for DTV/ATV/DAB/ANALOG AUDIO BROADCASTING media is provided, including a USB hub, at least a DTV/ATV/DAB/ANALOG AUDIO BROADCASTING interface converter, and a plurality of storage media interfaces. The upstream port of the USB hub is connected to a USB interface of an electronic device. The DTV/ATV/DAB/ANALOG AUDIO BROADCASTING interface converter and a plurality of storage media interfaces are connected respectively to the downstream ports of the USB hub. The DTV/ATV/DAB/ANALOG AUDIO BROADCASTING interface converter can convert DTV/ATV/DAB/ANALOG AUDIO BROADCASTING signals into data uploaded through the USB hub to the electronic device with the USB interface for playing. The electronic device can process the data, such as compression, filtering, and so on, and then downloads the processed data to each storage media interface, such as flash memory, CD-RW, DVD-RW, and hard disk, through the USB hub.

Abstract: The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.

Abstract: The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.

Abstract: First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as ?6V˜12V, ?12V˜6V, ?9V˜9V etc.

Abstract: First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

Abstract: A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.

Abstract: A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.

Abstract: A method for reducing a gate length bias is disclosed. The method utilizes an additional blanket ion implantation process to adjust the etching property of the undoped conductive layer such as a polysilicon layer used to form NMOS and PMOS gate electrodes so that the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes can be effectively reduced.

Abstract: A P-well and an N-well adjacent to the P-well are formed within a semiconductor substrate. A silicon nitride layer having an opening and a silicon oxide layer are then formed, respectively, on the semiconductor substrate. The silicon oxide layer fills the opening in the silicon nitride layer. Following that, a chemical mechanical polishing process removes portions of the silicon oxide layer to align the surface of the remaining silicon oxide layer with the surface of the silicon nitride layer to form an insulator. Subsequently, the silicon nitride layer is completely removed followed by forming a gate layer positioned on the P-well and N-well, a side of the gate layer being positioned on the surface of the insulator. Finally, an ion implantation process is performed to form N-type doping regions on the P-well and the N-well as a source and a drain of an LD MOS transistor, completing fabrication of the LD MOS transistor.

Abstract: A method of manufacturing the metallic electrodes of a capacitor in a mixed mode semiconductor device. The method comprises the steps of providing a substrate having a conductive layer and the lower electrode of a capacitor formed thereon, and then depositing a dielectric layer over the substrate. A first opening and a second opening are then formed in the dielectric layer. The first opening exposes a portion of the conductive layer while the second opening exposes a portion of the lower electrode. Finally, a conductive plug and the upper electrode of the capacitor are formed in the respective first and second openings that are in corresponding positions above the conductive layer and lower electrode, respectively.