Patents by Inventor Ching-Chun Hwang

Ching-Chun Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6638841
    Abstract: A method for reducing a gate length bias is disclosed. The method utilizes an additional blanket ion implantation process to adjust the etching property of the undoped conductive layer. According to the present invention, a polysilicon layer is used to form NMOS and PMOS gate electrodes so that the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes can be effectively reduced.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: October 28, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Jen Ko, Yuan-Li Tsai, Ming-Hui Wu, Steven Huang, Ching-Chun Hwang
  • Patent number: 6624079
    Abstract: The method for forming high voltage device combined with a mixed mode process use an un-doped polysilicon layer instead of the conventional polysilicon layer. In the high resistance area, the ion implant is not used until the source region and the drain region are formed. A resistor is formed by etching oxide-nitride-oxide layer and performing ion implant process by using BF2 radical to the un-doped polysilicon layer to control the resistance. Then multitudes of contact are formed, wherein the high dosage of BF2 implant would reduce resistance between contacts and resistor.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: September 23, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Yuan-Li Tsai, Marcus Yang, Ralph Chen, Heng-Chun Kao, Ching-Chun Hwang
  • Publication number: 20030036276
    Abstract: A method for forming a high resistance resistor with an integrated high voltage device process is disclosed. First and second field oxide areas are formed on a substrate and an undoped first polysilicon layer is deposited. A first photoresist layer having a resistor pattern is formed on the first field oxide area and a first ion implant process is performed with the first photoresist layer as a mask which is then removed and an oxide nitride oxide (ONO) layer is formed on the first polysilicon layer. The ONO layer and the first polysilicon layer are etched to form a resistor on the first field oxide area and a first electrode of a capacitor on the second field oxide area. A second polysilicon layer is formed on the capacitor ONO layer as a second electrode of the capacitor. A second photoresist layer is formed on the substrate, the resistor and the capacitor and has an opening pattern to expose the resistor. The ONO layer is removed from the resistor.
    Type: Application
    Filed: August 20, 2001
    Publication date: February 20, 2003
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Li Tsai, Marcus Yang, Ralph Chen, Heng-Chun Kao, Ching-Chun Hwang
  • Patent number: 6410377
    Abstract: The present invention provides a method for integrating the fabrication of a sensor and a high voltage devices. The N conductive type sensor has a P conductive type doped region in the substrate of the sensor active region to effectively reduce the leakage at edges of the field oxide. Furthermore, there are the P conductive type field and the P conductive type well used as isolations for the sensor and these isolations can prevent blooming. Between these isolations, high voltage devices can be simultaneously formed thereon.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: June 25, 2002
    Inventors: Ching-Chun Hwang, Sheng-Hsiung Yang
  • Patent number: 6268266
    Abstract: A method for forming enhanced field oxide (FOX) region of low voltage devices in a high voltage process is disclosed. The method includes providing a semiconductor structure comprising a substrate, two field oxide regions on the substrate, a well between the two field oxide regions in the substrate and a silicon nitride layer between the two field oxide regions above the well. As a key step, nitrogen is implanted into the semiconductor structure, and the silicon nitride layer is then removed. Then, a gate oxide layer on the well and silicon oxynitride layer on the field oxide regions are all formed in-situ.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: July 31, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Chun Hwang, Fei-Hung Chen, Meng-Jin Tsai, Wei-Chung Chen
  • Patent number: 6204129
    Abstract: A method for producing self-aligned silicidation, substantially facilitating the integration of the high-voltage and low-voltage MOS device, is disclosed. The method includes providing, the present invention provides a integration of high-voltage and low-voltage MOS transistor, which self-aligned silicidation process. A substrate is provided incorporating a device, wherein the device is defined high-voltage MOS region and low-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a MOS region. Moreover, a polysilicon layer is formed over said high-voltage MOS region and low-voltage MOS region, and a first dielectric layer is deposited above the polysilicon layer of the high-voltage MOS region and low-voltage MOS region.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: March 20, 2001
    Assignee: United Microelectronics Corp
    Inventors: Ching-Chun Hwang, Wei-Chung Chen, Chien-Kuo Yang
  • Patent number: 6117718
    Abstract: A method for forming bipolar junction transistor with high gain via formulation of high voltage device in deep submicron process is disclosed. A substrate including a first part, a second part, and a third part is primarily provided; then, a first well in the first part and a second well in the second part are formed. A plurality of field oxide regions are formed on said substrate; subsequently, two third wells are formed in said third part. The following steps are to form a fourth well in said first well in said first part and two fifth wells in said second well in said second part; and to form a first gate on said first part between said two third wells, and a second gate on said second part between said two fifth wells. Next, a first spacer against said first gate and a second spacer against said second gate are formed. Further, first ions are introduced into said first part to serve as a collector region, and into said third part to serve as a first source/drain region.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: September 12, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Chun Hwang, Sheng-Hsiung Yang