Abstract: A method of demodulating a square root for processing digital signals is disclosed. The demodulation includes the following steps. First, define |l arg e| to be the larger one between the absolute value of two input values I and Q and define |small| to be the smaller one between the absolute value of the two input values I and Q. Next, define a first determining form by the inequalities 16|small?16|l arg e|?18|small| and 16|l arg e|=16|small|. In addition, define a second determining form by the inequalities 16|small|?16|l arg e|?18|small| and 16|l arg e|?|small|. When the relation between |l arg e| and |small| conforms to the first determining form, the approximate root-mean-square value of the two input values I and Q is |l arg e|+2?5|l arg e|. When the relation between |l arg e| and |small| conforms to the second determining form, the approximate root-mean-square value of the two input values I and Q is |l arg e|+2?6|l arg e|.

Abstract: An extendable squarer for processing digital signals, suitable for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n?1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes of the n-bit data corresponding thereto according to the binary weight. In addition, except for bit code of the most-significant bit, the other operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention generates the square operation value of the n-bit data based on the corresponding bit expanding data and bit codes.

Abstract: An extendable squarer applied for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n?1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes of the n-bit data corresponding thereto according to the binary weight. In addition, except for bit code of the most-significant bit, the other operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention generates the square operation value of the n-bit data based on the corresponding bit expanding data and bit codes.

Abstract: A method for demodulating a square root is disclosed. The demodulation comprises the following steps. First, define |large| to be the larger one between the absolute value of two input values I and Q and define |small| to be the smaller one between the absolute value of the two input values I and Q. Next, define a first determining form by the inequalities 16|small|?16|large|?18|small| and 16|large|=16|small|. In addition, define a second determining form by the inequalities 16|small|?16|large|?18|small| and 16|large|?16|small|. When the relation between |large| and |small| conforms to the first determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2?5|large|. When the relation between |large| and |small| conforms to the second determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2?6|large|.

Abstract: An apparatus and method for demodulating a square root of the sum of squares of two inputs I and Q in a digital signal processing are provided. The square root {square root over (I2+Q2)} is approximated by an equation aX +bY, wherein coefficients a and b are special binary numbers. Due to the numbers, the square root {square root over (I2+Q2)} can be quickly computed by the operation of shifting and addition. A plurality of possible approximation values for the coefficients a and b are provided, as well as the use of a comparator to select the maximal one among the possible approximation values.