Abstract: A backside illuminated (BSI) image sensor device includes a device layer, a doped isolation region and a doped radiation sensing region. The device layer has a front side and a backside, in which the device layer has a thickness greater than or equal to 4 ?m. The doped isolation region having a first dopant of a first conductivity is through the device layer to define a plurality of pixel regions of the device layer, in which the doped isolation region includes a first upper region adjacent to the front side and a first lower region between the first upper region and the backside, and the first upper region has a width less than a width of the first lower region. The doped radiation sensing region having a second dopant of a second conductivity opposite to the first conductivity is in one of the pixel regions of the device layer.

Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may also be employed to promote topographic uniformity at wafer edges.

Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.

Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.

Abstract: In some embodiments, the present disclosure relates to a back-side image (BSI) sensor having a global shutter pixel with a reflective material that prevents contamination of a pixel-level memory node. In some embodiments, the BSI image sensor has an image sensing element arranged within a semiconductor substrate and a pixel-level memory node arranged within the semiconductor substrate at a location laterally offset from the image sensing element. A reflective material is also arranged within the semiconductor substrate at a location between the pixel-level memory node and a back-side of the semiconductor substrate. The reflective material has an aperture that overlies the image sensing element. The reflective material allows incident radiation to reach the image sensing element while preventing the incident radiation from reaching the pixel-level memory node, thereby preventing contamination of the pixel-level memory node.

Abstract: The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: Presented herein is a device comprising an image sensor having a plurality of pixels disposed in a substrate and configured to sense light through a back side of the substrate and an RDL disposed on a front side of the substrate and having a plurality of conductive elements disposed in one or more dielectric layers. A sensor shield is disposed over the back side of the substrate and extending over the image sensor. At least one via contacts the sensor shield and extends from the sensor shield through at least a portion of the RDL and contacts at least one of the plurality of conductive elements.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess. The second surface is opposite to the first surface. The recess passes through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer over the second surface. The semiconductor device structure includes a first bonding pad in the recess and extending to the first wiring layer so as to be electrically connected to the first wiring layer. The semiconductor device structure includes a nickel layer over the first bonding pad. The semiconductor device structure includes a gold layer over the nickel layer.

Abstract: A method includes forming a plurality of pixels formed on a front surface of a semiconductor substrate, forming an array of color filters over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels, forming a plurality of micro-lenses over the array of color filters, and forming a second layer between the pixels and the color filters. The second layer further includes a structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens, further wherein the plurality of micro-lenses are in contact with the array of color filters, and wherein the structure and the transparent material are coplanar at respective top surfaces thereof, and further wherein the structure directly contacts a bottom surface of at least one of the color filters.

Abstract: An image sensor structure and a method for forming the same are provided. The image sensor structure includes a first substrate including a first radiation sensing region and a first interconnect structure formed over a front side of the first substrate. The image sensor structure further includes a second substrate including a second radiation sensing region and a second interconnect structure formed over a front side of the second substrate. In addition, the first interconnect structure is bonded with the second interconnect structure.

Abstract: An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.

Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured to receive light in a first direction from a light source. An interconnect structure is disposed over the first substrate, and includes a plurality of metal layers and insulating layers that are over stacked over one another in alternating fashion. One of the plurality of metal layers is closest to the light source and another of the plurality of metal layers is furthest from the light source. A bond pad recess extends into the interconnect structure from an opening in a surface of the 3DIC which is nearest the light source and terminates at a bond pad. The bond pad is spaced apart from the surface of the 3DIC and is in direct contact with the one of the plurality of metal layers that is furthest from the light source.

Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.

Abstract: Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler grid portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler grid portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.

Abstract: Embodiments of the present disclosure include an image sensor device and methods of forming the same. An embodiment is an image sensor device including a first plurality of pickup regions in a photosensor array area of a substrate, each of first plurality of pickup regions having a first width and a first length, a second plurality of pickup regions in a periphery area of the substrate, the periphery area along at least one side of the photosensor array area, each of second plurality of pickup regions having a second width and a second length.

Abstract: An image sensor device includes a semiconductor substrate having a front surface and a back surface; an array of pixels formed on the front surface of the semiconductor substrate, each pixel being adapted for sensing light radiation; an array of color filters formed over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels; and an array of micro-lens formed over the array of color filters, each micro-lens being adapted for directing light radiation to at least one of the color filters in the array. The array of color filters includes structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens.