Patents by Inventor Ching-Chun YEH

Ching-Chun YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140782
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: PO CHEN YEH, YI-HSIEN CHANG, FU-CHUN HUANG, CHING-HUI LIN, CHIAHUNG LIU, SHIH-FEN HUANG, CHUN-REN CHENG
  • Publication number: 20240127987
    Abstract: An integrated over-current protection device includes a positive temperature coefficient (PTC) component, a first conductive unit, a second conductive unit, a first conductive via, and a second conductive via. The PTC component includes a first PTC body, and has opposing first and second surfaces. The first conductive unit is disposed on the first surface, and includes a first electrode and a first conductive pad electrically insulated from the first electrode. The second conductive unit is disposed on the second surface, and includes a second electrode and a second conductive pad electrically insulated from the second electrode. The first conductive via extends through the first conductive unit and the PTC component to electrically connect the first electrode to the second conductive pad. The second conductive via extends through the second conductive unit and the PTC component to electrically connect the second electrode to the first conductive pad.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Inventors: Jack Jih-Sang CHEN, Chang-Hung JIANG, Ching-Chiang YEH, Ming-Chun LEE
  • Publication number: 20180013018
    Abstract: A solar cell includes a semiconductor substrate, a bus-bar electrode, a plurality of finger electrodes, and a heavily doped layer. The semiconductor substrate has a surface. The bus-bar electrode is on the surface of the semiconductor substrate and extending along a first direction. The finger electrodes are on the surface of the semiconductor substrate and extending along a second direction. One of two ends of each of the finger electrodes is connected to the bus-bar electrode. An angle created by the first direction and the second direction is less than 180 degrees. The heavily doped layer is formed on the surface of the semiconductor substrate and includes a first portion and a plurality of second portions. The first portion is extending along the first direction. Each of the second portions is extending from the first portion along the second direction and beneath the corresponding finger electrode.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 11, 2018
    Applicant: NEO SOLAR POWER CORP.
    Inventors: Shan-Chuang PEI, Ching-Chun YEH, Wei-Chih HSU
  • Publication number: 20150129022
    Abstract: A back contact solar cell includes a solar cell substrate, an intrinsic layer, a second conductive type semiconductor layer and an electrode layer. The solar cell substrate includes a substrate body doped with a first conductive type semiconductor and a plurality of first conductive type semiconductor doped regions. The first conductive type semiconductor doped region is formed on a back side of the substrate body. The intrinsic layer is formed on the back side, and includes a plurality of first openings to expose the first conductive type semiconductor doped regions. The second conductive type semiconductor layer is deposited on the intrinsic layer, and includes a plurality of second openings correspond the first openings. The electrode layer includes a plurality of first electrode regions and a second electrode region. The first electrode regions are disposed on the first conductive type semiconductor doped regions.
    Type: Application
    Filed: June 24, 2014
    Publication date: May 14, 2015
    Inventors: Chorngjye HUANG, Feng-Yu YANG, Shan-Chuang PEI, Ching-Chun YEH, Tien-Shao CHUANG