Abstract: A semiconductor device includes a substrate having an active region, a recessed region in the active region, a gate dielectric layer on the substrate in the recessed region, a gate structure on the gate dielectric layer, and a doped region in the active region at two sides of the recessed region, wherein a depth of the recessed region is smaller than a depth of the doped region.

Abstract: Embodiments of the present disclosure relate to methods of fabricating conductive features to prevent metal extrusion. Particularly, the conductive feature includes a control layer to reduce grain size of a metal containing layer, thus obtaining a robust structure to decrease extrusion defects. In some embodiments, the control layer is formed between a barrier layer and the conductive feature. In some embodiments, the control layer is formed by adding a control element, such as oxygen, to an upper portion of the barrier layer.

Abstract: A method of converting waste into energy is provided. The method includes the following steps: (a) providing a lipid-containing substrate to react with a biocatalyst to produce a surfactant molecular liquid; (b) pretreating an organic waste with the surfactant molecular liquid to produce a first organic liquid; (c) subjecting the first organic liquid to an ultrasonic treatment to produce a second organic liquid; and (d) subjecting the second organic liquid to an anaerobic biological treatment for conversion to methane. The biocatalyst includes at least one lipase. Moreover, the surfactant molecular liquid includes at least one of monoglyceride and diglyceride. A waste treatment system for converting waste into energy is also provided.

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, a control layer disposed over the first ILD layer and containing silicon and oxygen, and a resistor wire disposed over the control layer. An oxygen concentration of the control layer is greater than an oxygen concentration of the first ILD layer.

Abstract: Semiconductor device isolation is provided. In one aspect, a semiconductor device include a spiral inductor. The semiconductor device includes a patterned ground shield (PGS) electrically coupled with the spiral inductor. The semiconductor device includes a filter configured to exchange energy with the PGS. The semiconductor device includes a circuit vertically spaced from the inductor, the PGS disposed between the circuit and the spiral inductor.

Abstract: An image sensor includes a plurality of pixels. Each of the plurality of pixels includes a photodiode. Each pixel further includes a color filter over the photodiode. Each pixel further includes a first transparent conductive layer over the color filter. Each pixel further includes an electro-optical (EO) film over the first transparent conductive layer. Each pixel further includes a second transparent conductive layer over the EO film. Each pixel further includes a pillar of transparent conductive material electrically connecting the first transparent conductive layer and the second transparent conductive layer.

Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region comprises multiple alternating well layers and first barrier layers, wherein each of the first barrier layers has a band gap, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; a first electron blocking layer between the second semiconductor structure and the active region, wherein the first electron blocking layer having a band gap greater than the band gap of one of the first barrier layers; a first aluminum-containing layer between the first electron blocking layer and the active region, wherein the first aluminum-containing layer has a first thickness and a band gap greater than the band gap of the first electron blocking layer; and a second aluminum-conta

Abstract: A semiconductor device includes a substrate of first conductivity type; a first heavily doped region and a second heavily doped region of second conductivity type spaced apart from the first heavily doped region, located in the substrate; a channel region in the substrate and between the first heavily doped region and the second heavily doped region; a gate disposed on the channel region; a hard mask layer covering a top surface and a sidewall of the gate; and a spacer disposed on a sidewall of the hard mask layer.

Abstract: A transistor structure including a substrate, a gate dielectric layer, a gate, a first doped region, a second doped region, a first drift region, and a dummy gate is provided. The gate dielectric layer is located on the substrate. The gate dielectric layer includes first and second portions. The second portion is connected to the first portion. The thickness of the second portion is greater than the thickness of the first portion. The gate is located on the first and second portions. The first doped region and the second doped region are located in the substrate on two sides of the gate dielectric layer. The first drift region is located in the substrate on one side of the gate. The second doped region is located in the first drift region. The dummy gate is located on the second portion between the gate and the second doped region.

Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.

Abstract: A drug conjugate includes a structure shown by the following formula: Z-(linker-[R]m)n. In the formula, Z is a drug compound, R is a sugar, and m and n are independently an integer from 1 to 6. The drug compound Z is a hepatitis virus targeting drug, a hepatitis B virus (HBV) drug, an inhibitor of apoptosis protein (IAP) antagonist, a multidrug resistance (MDR) inhibitor, or analogues, precursors, prodrugs, derivatives thereof.

Abstract: A semiconductor structure includes a substrate comprising a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region, wherein the first conductive type and the second conductive type are complementary. An isolation structure is formed in the substrate to define a plurality of first dummy diffusions and second dummy diffusions and at least a first active region in the first well region, wherein the first dummy diffusions are adjacent to the junction, the first dummy diffusions are between the second dummy diffusions and the first active region, and wherein the second dummy diffusions respectively comprise a metal silicide portion. A plurality of first dummy gates are disposed on the first dummy diffusions and completely cover the first dummy diffusions, respectively.

Abstract: An image sensor includes a first photodiode and a second photodiode. The image sensor further includes a first color filter over the first photodiode; and a second color filter over the second photodiode. The image sensor further includes a first microlens over the first color filter and a second microlens over the second color filter. The image sensor further includes a first electro-optical (EO) film between the first color filter and the first microlens, wherein a material of the first EO film is configured to change refractive index in response to application of an electrical field. The image sensor further includes a second EO film between the second color filter and the second microlens, wherein a material of the second EO film is configured to change refractive index in response to application of an electrical field.

Abstract: A semiconductor electrochemical plating (ECP) tool includes: a plating cell which receives an ECP solution therein; a support onto which a semiconductor substrate is selectively secured, the support being controllable to selectively dip the semiconductor substrate into ECP solution contained in the plating cell; a recirculation system including a reservoir that receives an overflow of ECP solution from the plating cell, the ECP solution being recirculated from the reservoir back to the plating cell; a bubble monitoring system that detects gas bubbles within the ECP solution; and a degassing system that inhibits at least one of gas bubble formation, nucleation and growth within the ECP solution, wherein the degassing system is controlled at least in part based upon gas bubble detection by the bubble monitoring system.

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.

Abstract: Some implementations described herein provide techniques and apparatuses for forming a copper structure adjacent to a multi-layer film structure included in a semiconductor device. The techniques include using an electroplating process to form the copper structure adjacent to the multi-layer film structure, wherein a pre-layer of chlorine molecules coats a seed layer of the multi-layer film structure during the electroplating process. During formation of the copper structure, a chlorine-enriched interface region (e.g., a control layer including a copper chelate material with chlorine) may be formed between the copper structure and the multi-layer film structure including the seed layer. The chlorine-enriched interface region may reduce a likelihood of electromigration and/or stress migration within the semiconductor device.

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

Abstract: A buffer layer may be included between a first conductive electrode layer and an insulator layer, and/or between a second conductive electrode layer and the insulator layer of a capacitor structure to reduce lattice mismatching in the capacitor structure. The buffer layer(s) include a combination of materials that promote lattice matching between the insulator layer and one or more of the conductive electrode layers. This reduces the likelihood of formation of structural defects in the capacitor structure relative to another capacitor structure that does not include the buffer layers.