Patents by Inventor Ching-Chung Hsu
Ching-Chung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11976170Abstract: The present invention provides a polybenzoxazole precursor, which comprises a structure of formula (I): wherein the definitions of Y, Z, R1, i, j, and V are provided herein. By means of the polybenzoxazole precursor, the resin composition of the present invention is able to form a film with high frequency characteristics and high contrast.Type: GrantFiled: July 5, 2022Date of Patent: May 7, 2024Assignee: MICROCOSM TECHNOLOGY CO., LTD.Inventors: Steve Lien-chung Hsu, Yu-Ching Lin, Yu-Chiao Shih, Hou-Chieh Cheng
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Patent number: 11670584Abstract: The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.Type: GrantFiled: August 3, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Ching-Chung Hsu, Chung-Long Chang
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Patent number: 11264378Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.Type: GrantFiled: December 20, 2019Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Yu Chen, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
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Publication number: 20210366828Abstract: The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: CHEN-FA LU, CHENG-YUAN TSAI, CHING-CHUNG HSU, CHUNG-LONG CHANG
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Patent number: 11114378Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.Type: GrantFiled: April 19, 2019Date of Patent: September 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Ching-Chung Hsu, Chung-Long Chang
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Patent number: 10879342Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.Type: GrantFiled: May 21, 2020Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
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Publication number: 20200286981Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.Type: ApplicationFiled: May 21, 2020Publication date: September 10, 2020Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
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Patent number: 10672860Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.Type: GrantFiled: September 30, 2019Date of Patent: June 2, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
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Publication number: 20200126976Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Yu CHEN, Chih-Ping CHAO, Chun-Hung CHEN, Chung-Long CHANG, Kuan-Chi TSAI, Wei-Kung TSAI, Hsiang-Chi CHEN, Ching-Chung HSU, Cheng-Chang HSU, Yi-Sin WANG
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Publication number: 20200066831Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.Type: ApplicationFiled: September 30, 2019Publication date: February 27, 2020Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
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Patent number: 10515949Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.Type: GrantFiled: October 17, 2013Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Yu Chen, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
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Patent number: 10475877Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.Type: GrantFiled: August 21, 2018Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
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Publication number: 20190252317Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.Type: ApplicationFiled: April 19, 2019Publication date: August 15, 2019Inventors: CHEN-FA LU, CHENG-YUAN TSAI, CHING-CHUNG HSU, CHUNG-LONG CHANG
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Patent number: 10269701Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.Type: GrantFiled: October 2, 2015Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Ching-Chung Hsu, Chung-Long Chang
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Publication number: 20170098606Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.Type: ApplicationFiled: October 2, 2015Publication date: April 6, 2017Inventors: CHEN-FA LU, CHENG-YUAN TSAI, CHING-CHUNG HSU, CHUNG-LONG CHANG
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Publication number: 20150108607Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Yu CHEN, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
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Patent number: 8967803Abstract: An image capturing apparatus and an auto-focusing method thereof are provided. The method includes transmitting light beams from light sources to an eye including a cornea, a pupil, a crystalline lens, and a fundus. The light beams are transmitted to the fundus through the cornea. The light beams transmitted to the cornea form first light point images detected by an image sensor through a lens module having first and second lenses. According to the first light point images and focal adjustment data, the first lens and the light sources are moved simultaneously to focus on the cornea. The light beams are substantially intersected at the pupil and transmitted to the fundus to form second light point images detected by the image sensor through the lens module. According to the second light point images and the focal adjustment data, the first lens is moved to focus on the fundus.Type: GrantFiled: September 7, 2012Date of Patent: March 3, 2015Assignee: Altek CorporationInventors: Tso-Yu Chang, Yu-Fen Chung, Te-Chao Tsao, Pin-Wen Chen, Shin-Hao Cheng, Peng-Hsiang Wang, Ching-Chung Hsu, Chun-An Lin
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Publication number: 20140085607Abstract: An image detecting apparatus for detecting a first eyeball is provided. The image detecting apparatus includes an illumination light source, an imaging lens, an image sensing device, a display and a viewfinder. The illumination light source emits an illumination beam, and the illumination beam irradiates the first eyeball. The first eyeball reflects the illumination beam into an image beam. The imaging lens is disposed on a transmission path of the image beam. The image sensing device is disposed on the transmission path of the image beam, wherein the imaging lens is disposed between the first eyeball and the image sensing device. The display shows the image formed by the image beam. The viewfinder is disposed in front of the display such that a second eyeball observes the display via the viewfinder. An image detecting method is also provided.Type: ApplicationFiled: December 18, 2012Publication date: March 27, 2014Applicant: ALTEK CORPORATIONInventors: Pin-Wen Chen, Ching-Chung Hsu, Tso-Yu Chang, Chung-Ping Lai
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Publication number: 20140016092Abstract: An image capturing apparatus and an auto-focusing method thereof are provided. The method includes transmitting light beams from light sources to an eye including a cornea, a pupil, a crystalline lens, and a fundus. The light beams are transmitted to the fundus through the cornea. The light beams transmitted to the cornea form first light point images detected by an image sensor through a lens module having first and second lenses. According to the first light point images and focal adjustment data, the first lens and the light sources are moved simultaneously to focus on the cornea. The light beams are substantially intersected at the pupil and transmitted to the fundus to form second light point images detected by the image sensor through the lens module. According to the second light point images and the focal adjustment data, the first lens is moved to focus on the fundus.Type: ApplicationFiled: September 7, 2012Publication date: January 16, 2014Applicant: ALTEK CORPORATIONInventors: Tso-Yu Chang, Yu-Fen Chung, Te-Chao Tsao, Pin-Wen Chen, Shin-Hao Cheng, Peng-Hsiang Wang, Ching-Chung Hsu, Chun-An Lin
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Patent number: 8596505Abstract: A detachable accessory carrier for bicycle includes a fixed seat, a positioning member and a fastener. The fixed seat has a positioning portion and a fixing portion communicated mutually. The positioning member has an inserting portion that includes a propping portion corresponding to the fixing portion so that when the inserting portion of the positioning member is assembled to the positioning portion of the fixed seat, the fastener can be coupled with the fixing portion and abut against the propping portion of the positioning member, thereby attaching the detachable accessory carrier reliably to the frame tube of the bicycle. The detachable accessory carrier can be partially detached with only the fixed seat left on the frame tube of the bicycle. The fixed seat has a rim conforming to a periphery of the frame tube so it will not interfere with the cyclist's riding or scrape the cyclist's skin.Type: GrantFiled: September 7, 2011Date of Patent: December 3, 2013Assignees: Flybikes S.L.Inventor: Ching-Chung Hsu