Patents by Inventor Ching-Chung Ko
Ching-Chung Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079444Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.Type: ApplicationFiled: June 12, 2023Publication date: March 7, 2024Applicant: MediaTek Inc.Inventors: Zheng Zeng, Ching-Chung Ko, Kuei-Ti Chan
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Publication number: 20240077802Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate. The protective layer and the photoresist layer are selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer. The protective layer includes a polymer without a nitrogen-containing moiety, and a basic quencher, an organic acid, a photoacid generator, or a thermal acid generator.Type: ApplicationFiled: August 7, 2023Publication date: March 7, 2024Inventors: Yu-Chung SU, Tsung-Han KO, Ching-Yu CHANG
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Patent number: 11715754Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.Type: GrantFiled: May 12, 2021Date of Patent: August 1, 2023Assignee: MediaTek Inc.Inventors: Zheng Zeng, Ching-Chung Ko, Kuei-Ti Chan
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Publication number: 20220357211Abstract: The present invention provides a processing circuit including logic cells and a thermal sensor. The thermal sensor is positioned within the logic cells and surrounded by the logic cells, and the logic cells and the thermal sensor are all implemented by core devices.Type: ApplicationFiled: April 13, 2022Publication date: November 10, 2022Applicant: MEDIATEK INC.Inventors: Min-Hang Hsieh, Jyun-Jia Huang, Chien-Sheng Chao, Ghien-An Shih, Ching-Chung Ko, Yu-Cheng Su, Lin-Chien Chen, Ai-Yun Liu, Chia-Hsin Hu
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Patent number: 11367788Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.Type: GrantFiled: April 21, 2020Date of Patent: June 21, 2022Assignee: MEDIATEK INC.Inventors: Jing-Chyi Liao, Ching-Chung Ko, Zheng Zeng
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Publication number: 20210384291Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.Type: ApplicationFiled: May 12, 2021Publication date: December 9, 2021Inventors: Zheng Zeng, Ching-Chung Ko, Kuei-Ti Chan
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Publication number: 20200373428Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.Type: ApplicationFiled: April 21, 2020Publication date: November 26, 2020Inventors: Jing-Chyi LIAO, Ching-Chung KO, Zheng ZENG
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Patent number: 10002833Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.Type: GrantFiled: May 25, 2017Date of Patent: June 19, 2018Assignee: MediaTek Inc.Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
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Patent number: 9972673Abstract: The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.Type: GrantFiled: March 27, 2017Date of Patent: May 15, 2018Assignee: MEDIATEK INC.Inventors: Zheng Zeng, Ching-Chung Ko, Bo-Shih Huang
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Patent number: 9893049Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region, a first well region having a first conductive type formed in the active region, a first doped region having the first conductive type formed in the first well region, a first metal contact disposed on the first doped region, and a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.Type: GrantFiled: February 25, 2015Date of Patent: February 13, 2018Assignee: MEDIATEK INC.Inventors: Zheng Zeng, Ching-Chung Ko, Bo-Shih Huang
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Publication number: 20170263559Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Applicant: MediaTek Inc.Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
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Publication number: 20170200783Abstract: The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Inventors: Zheng ZENG, Ching-Chung KO, Bo-Shih HUANG
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Patent number: 9698102Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.Type: GrantFiled: May 31, 2016Date of Patent: July 4, 2017Assignee: MediaTek Inc.Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
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Publication number: 20160276274Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.Type: ApplicationFiled: May 31, 2016Publication date: September 22, 2016Inventors: Ching-Chung KO, Tao CHENG, Tien-Yueh LIU, Ta-Hsi CHOU, Peng-Cheng KAO, Ling-Wei KE
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Patent number: 9379059Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.Type: GrantFiled: November 1, 2011Date of Patent: June 28, 2016Assignee: MEDIATEK INC.Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
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Patent number: 9324705Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.Type: GrantFiled: January 22, 2014Date of Patent: April 26, 2016Assignee: MEDIATEK INC.Inventors: Ching-Chung Ko, Tung-Hsing Lee
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Publication number: 20150171072Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region, a first well region having a first conductive type formed in the active region, a first doped region having the first conductive type formed in the first well region, a first metal contact disposed on the first doped region, and a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.Type: ApplicationFiled: February 25, 2015Publication date: June 18, 2015Inventors: Zheng ZENG, Ching-Chung KO, Bo-Shih HUANG
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Patent number: 8860544Abstract: An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.Type: GrantFiled: June 29, 2009Date of Patent: October 14, 2014Assignee: Mediatek Inc.Inventors: Ching-Chung Ko, Tung-Hsing Lee, Kuei-Ti Chan, Tao Cheng, Ming-Tzong Yang
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Patent number: 8836043Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.Type: GrantFiled: January 22, 2014Date of Patent: September 16, 2014Assignee: Mediatek Inc.Inventors: Ching-Chung Ko, Tung-Hsing Lee
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Publication number: 20140224653Abstract: Provided is a silver nanowire-containing composition for a biosensor strip, a biosensor strip comprising the same and its preparation method. The biosensor strip comprises a conductive pattern layer made of the silver nanowire-containing composition. With the aspect ratio of 50 to 500, the silver nanowire-containing composition has good dispersion and high conductivity, such that the biosensor strip comprising the same can have high stability and provide a more accurate and efficient detection.Type: ApplicationFiled: January 29, 2014Publication date: August 14, 2014Applicants: Industrial Technology Research Institute, K Cubic Research Co., Ltd.Inventors: Wen-Hsien Sun, Hou-Yu Lee, Shyh-Dar Ko, Ching-Chung Ko