Abstract: A data copying method for one-to-many reproduction apparatus having a data buffer includes steps of: reading multiple data segments from source data into the data buffer, detecting newly connected random access devices, selecting the data segments from the data buffer individually for each of the random access devices, copying the respectively selected data segments into each of the random access devices, and determining whether each of the data segments in the data buffer has been copied into all the random access devices and whether any of the random access devices has stored all the data segments of the source data. Newly connected devices are allowable to improve efficiency. Segment selection prevents multiple devices from writing identical data synchronously and thereby prevents accumulation of identical electromagnetic leakage. Consequently, electromagnetic interference is reduced.

Abstract: An operational amplifier includes a first stage, a second stage, and a switching unit. The first stage receives an analog input signal. The second stage has an output node coupled to an output switch. The switching unit is coupled between the first stage and the second stage. The switching unit includes a capacitive component and a first switch coupled to the capacitive component in series. The first switch is turned off when the output switch is turned on. The first switch is turned off while the analog input signal is in transition, and is turned on while the analog input signal is steady. The first switch is turned on when the output switch is turned off.

Abstract: A data copying method for one-to-many reproduction apparatus having a data buffer includes steps of: reading multiple data segments from source data into the data buffer, detecting newly connected random access devices, selecting the data segments from the data buffer individually for each of the random access devices, copying the respectively selected data segments into each of the random access devices, and determining whether each of the data segments in the data buffer has been copied into all the random access devices and whether any of the random access devices has stored all the data segments of the source data. Newly connected devices are allowable to improve efficiency. Segment selection prevents multiple devices from writing identical data synchronously and thereby prevents accumulation of identical electromagnetic leakage. Consequently electromagnetic interference reduces.

Abstract: An output buffer and a source driver for a display panel are provided. The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage. The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal. The bias module provides a bias current to the differential input stage. The output stage has a second output terminal coupled to the first input terminal for providing an output current to the second output terminal based on a signal of the first output terminal. The feedback module adjusts the bias current and the output current based on the first input signal and the second input signal. The output buffer has ability of switching the output voltage to be low level and high level in high-speed.

Abstract: A reset circuit and a delay circuit are provided. The delay circuit includes a first resistor module, a second resistor module, a switch module and a capacitor module. First terminals of the first and the second resistor modules are coupled respectively to a first voltage and a second voltage. The switch module have a control terminal served as a input terminal of the delay circuit, a first terminal served as a output terminal of the delay circuit, a second terminal coupled to a second terminal of the first resistor module, and a third terminal coupled to a second terminal of the second resistor module. In the delay circuit, the first terminal selectively connected to the second terminal or the third terminal in accordance with the control terminal. The capacitor module couples between the first terminal of the switch module and the second voltage.

Abstract: An output buffering circuit of a driver device for a display includes a first amplifier circuit having a first input stage, coupled between an upper power supply and a lower power supply, and a first output stage, coupled between the upper power supply and a first intermediate power supply that is greater than the lower power supply, and a second amplifier circuit having a second input stage coupled between the upper power supply and the lower power supply, and a second output stage coupled between a second intermediate power supply that is lower than the upper power supply and the lower power supply.

Abstract: A digital to analog converter with two outputs controlled by an input signal with n-bits is disclosed. A reference voltage circuit generates (2n+1) reference voltages numbered from 1 to (2n+1). A switch array coupled to the reference voltage circuit, a first output terminal, and a second output terminal, includes a plurality of switches switching according to the input signal. The first output terminal outputs only one of odd reference voltages according to the input signal, and the second output terminal outputs one of even reference voltages according to the input signal, and the number of the switches is less than (n×2n+2n).

Abstract: A digital to analog converter with two outputs controlled by an input signal with n-bits is disclosed. A reference voltage circuit generates (2n+1) reference voltages numbered from 1 to (2n+1). A switch array coupled to the reference voltage circuit, a first output terminal, and a second output terminal, includes a plurality of switches switching according to the input signal. The first output terminal outputs only one of odd reference voltages according to the input signal, and the second output terminal outputs one of even reference voltages according to the input signal, and the number of the switches is less than (n×2n+2n).

Abstract: A reset circuit and a delay circuit are provided. The delay circuit includes a first resistor module, a second resistor module, a switch module and a capacitor module. First terminals of the first and the second resistor modules are coupled respectively to a first voltage and a second voltage. The switch module have a control terminal served as a input terminal of the delay circuit, a first terminal served as a output terminal of the delay circuit, a second terminal coupled to a second terminal of the first resistor module, and a third terminal coupled to a second terminal of the second resistor module. In the delay circuit, the first terminal selectively connected to the second terminal or the third terminal in accordance with the control terminal. The capacitor module couples between the first terminal of the switch module and the second voltage.

Abstract: An embodiment of a digital to analog converter (DAC) with two outputs is provided. The DAC is controlled by an n-bits input signal and comprises a reference voltage circuit generating (2n+1) reference voltages, a first switch array and a second switch array. The first switch array receives and outputs 2n selected reference voltages among the (2n+1) reference voltages to the second switch array. The second switch array outputs a first voltage via a first output terminal and a second voltage via a second output terminal according to the input signal, wherein the (2i+1)th reference voltages are directly transmitted to the second switch array, and when the first bit of the input signal is at a first voltage level, the first voltage is transmitted to the second output terminal, and the second voltage is transmitted to the first output terminal.

Abstract: An embodiment of a digital to analog converter (DAC) with two outputs is provided. The DAC is controlled by an n-bits input signal and comprises a reference voltage circuit generating (2n+1) reference voltages, a first switch array and a second switch array. The first switch array receives and outputs 2n selected reference voltages among the (2n+1) reference voltages to the second switch array. The second switch array outputs a first voltage via a first output terminal and a second voltage via a second output terminal according to the input signal, wherein the (2i+1)th reference voltages are directly transmitted to the second switch array, and when the first bit of the input signal is at a first voltage level, the first voltage is transmitted to the second output terminal, and the second voltage is transmitted to the first output terminal.

Abstract: A source driver includes an external data bus and a receiver configured to receive data signals from the external data bus, the receiver having an encoder configured to encode the data signals and output encoded signals such that a toggling rate of the encoded signals is less than a toggling rate of the data signals, an internal data bus configured to transmit the encoded signals, and a plurality of driving channels configured to receive the encoded signals from the internal data bus and to output driving voltages.

Abstract: An operational amplifier includes an amplifying circuit and a bais current generating circuit. The bias current generating circuit generates a bias current to the amplifying circuit. The amplifying circuit comprises a current adjusting unit and a current mirror. The current adjusting circuit has a storage element, receives a reference current and generating a passing current. The passing current is gradually adjusted utilizing the storage element according to a control signal. The current mirror receives the passing current to generate the bias current.

Abstract: An output buffering circuit of a driver device for a display includes a first amplifier circuit having a first input stage, coupled between an upper power supply and a lower power supply, and a first output stage, coupled between the upper power supply and a first intermediate power supply that is greater than the lower power supply, and a second amplifier circuit having a second input stage coupled between the upper power supply and the lower power supply, and a second output stage coupled between a second intermediate power supply that is lower than the upper power supply and the lower power supply.

Abstract: An operational amplifier includes a first stage, a second stage, and a switching unit. The first stage receives an analog input signal. The second stage has an output node coupled to an output switch. The switching unit is coupled between the first stage and the second stage. The switching unit includes a capacitive component and a first switch coupled to the capacitive component in series. The first switch is turned off when the output switch is turned on. The first switch is turned off while the analog input signal is in transition, and is turned on while the analog input signal is steady. The first switch is turned on when the output switch is turned off.

Abstract: A DAC includes a gamma voltage generator for generating a plurality of gamma voltages, and a decoder for receiving an M-bit digital value for selecting one of the gamma voltages, wherein the decoder comprises a first thermometer encoder, a first selector and a second selector. The first thermometer encoder is utilized to receive N bits of the digital value to generate a first thermometer code with 2N bits, wherein N is smaller than M, and M and N are positive integers. The first selector has a plurality of selecting groups, each selecting group having 2N switches controlled by the first thermometer code to output one gamma voltage, where the second selector receives the gamma voltages outputted by the selecting groups of the first selector and outputs one gamma voltage selected from the received gamma voltages based on the (M?N) bit of the digital value.

Abstract: A DAC includes a gamma voltage generator for generating a plurality of gamma voltages, and a decoder for receiving an M-bit digital value for selecting one of the gamma voltages, wherein the decoder comprises a first thermometer encoder, a first selector and a second selector. The first thermometer encoder is utilized to receive N bits of the digital value to generate a first thermometer code with 2N bits, wherein N is smaller than M, and M and N are positive integers. The first selector has a plurality of selecting groups, each selecting group having 2N switches controlled by the first thermometer code to output one gamma voltage, where the second selector receives the gamma voltages outputted by the selecting groups of the first selector and outputs one gamma voltage selected from the received gamma voltages based on the (M?N) bit of the digital value.

Abstract: An output buffer and a source driver for a display panel are provided. The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage. The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal. The bias module provides a bias current to the differential input stage. The output stage has a second output terminal coupled to the first input terminal for providing an output current to the second output terminal based on a signal of the first output terminal. The feedback module adjusts the bias current and the output current based on the first input signal and the second input signal. The output buffer has ability of switching the output voltage to be low level and high level in high-speed.

Abstract: During transition, level shifters in a source driver output logic high signals to PMOS DACs and output logic low signals to NMOS DACs for shutting down current paths in the PMOS DACs and in the NMOS DACs. Therefore, during transition, the PMOS DACs and the NMOS DACs are at high-impedance stage for preventing gamma coupling effect.

Abstract: During transition, level shifters in a source driver output logic high signals to PMOS DACs and output logic low signals to NMOS DACs for shutting down current paths in the PMOS DACs and in the NMOS DACs. Therefore, during transition, the PMOS DACs and the NMOS DACs are at high-impedance stage for preventing gamma coupling effect.