Abstract: A circuit-test probe card and a probe substrate structure thereof are disclosed herein to effectively narrow down the pitch of testing points of the circuit-test probe card. The circuit-test probe card utilizes the top and bottom surfaces of the probe substrate to respectively electrically connect with a circuit board and a plurality of probes. The probe substrate includes a main body having a plurality of upper contacts arranged on an upper surface thereof; and a plurality of wires penetrating the main body. Two ends of each wire are respectively exposed on the upper surface and a lower surface of the main body. The pitch of the wires exposed on the upper surface is larger than the pitch of the wires exposed on the lower surface. The wires are respectively electrically connected with the upper contacts.

Abstract: A polysilicon silicide electric fuse device, comprising: a substrate; a semiconductor material layer disposed on said substrate, said semiconductor material layer includes lead-out areas of the same doping type at both ends, and an intermediate area of non-doping or having dopant concentration lower than those of said lead-out areas at both ends; and one or more burn-out areas is/are provided in said intermediate area; and a metal silicide layer is provided on said semiconductor material layer. Through the application of said polysilicon silicide electric fuse device, the burning out of said fuse device is thus controlled to within said intermediate area of no doping or light doping, hereby increasing the mean value and reducing distribution area of electrical resistance after burning out of a fuse, and alleviating the overheating of surrounding areas as caused by a current during the burning out of a fuse.

Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.

Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.

Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.