Patents by Inventor Ching Dong Wang

Ching Dong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit memory system with dummy active region
    Patent number: 7332378
    Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.
    Type: Grant
    Filed: March 4, 2006
    Date of Patent: February 19, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sung Mun Jung, Ching Dong Wang, Louis Yoke Leng Lim, Swee Tuck Woo, Donghua Liu, Xiaoyu Chen
  • INTEGRATED CIRCUIT MEMORY SYSTEM WITH DUMMY ACTIVE REGION
    Publication number: 20070207558
    Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.
    Type: Application
    Filed: March 4, 2006
    Publication date: September 6, 2007
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Sung Mun Jung, Ching Dong Wang, Louis Yoke Leng Lim, Swee Tuck Woo, Donghua Liu, Xiaoyu Chen
  • Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate
    Patent number: 6764905
    Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: July 20, 2004
    Assignee: Integrated Memory Technologies, Inc.
    Inventors: Ching-Shi Jeng, Ching Dong Wang
  • METHOD OF MANUFACTURING A SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE
    Publication number: 20040105319
    Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.
    Type: Application
    Filed: July 9, 2003
    Publication date: June 3, 2004
    Inventors: Ching-Shi Jeng, Ching Dong Wang
  • Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate
    Patent number: 6621115
    Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: September 16, 2003
    Assignee: Integrated Memory Technologies, Inc.
    Inventors: Ching-Shi Jenq, Ching Dong Wang
  • Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate, and method of manufacturing the same
    Publication number: 20030087493
    Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.
    Type: Application
    Filed: November 6, 2001
    Publication date: May 8, 2003
    Inventors: Ching-Shi Jenq, Ching Dong Wang