Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Abstract: A method of etching a metal line. A substrate with a metal layer to be etched is provided, on which an amorphous carbon doped layer is formed over the metal layer by plasma enhanced chemical vapor deposition (PECVD). A resist layer is formed over the amorphous carbon doped layer, and the resist layer is patterned to define a resist mask. The amorphous carbon doped layer is etched to define a hardmask, the resist mask is stripped, and the metal layer not covered by the hardmask is etched to form a metal line for forming an interconnect.

Abstract: A method of etching a low-k dielectric layer. A substrate having a low-k dielectric layer to be etched, on which an amorphous carbon doped layer is formed over the low-k dielectric layer by plasma enhanced chemical vapor deposition (PECVD), a resist layer is formed over the amorphous carbon doped layer , and the resist layer is patterned to define a first opening thereby forming a resist mask. The amorphous carbon doped layer is etched to define a second opening, thereby forming a hardmask, the resist mask is stripped, and the low-k dielectric layer not covered by the hardmask is etched to form a third opening as a trench or via.

Abstract: A method to fabricate an interconnect structure is provided. First, an inter-metal dielectric layer is formed on a substrate. Then the inter-metal dielectric layer is etched to form a trench, and a barrier layer is formed on the trench. After, a metal layer is formed to fill in the trench over the barrier layer. Then a chemical mechanical polishing (CMP) process is performed to remove the barrier layer and the metal layer on the inter-metal dielectric layer. Finally, a conductive sealing layer is formed to cover the metal layer.