Abstract: A method of etching a metal line. A substrate with a metal layer to be etched is provided, on which an amorphous carbon doped layer is formed over the metal layer by plasma enhanced chemical vapor deposition (PECVD). A resist layer is formed over the amorphous carbon doped layer, and the resist layer is patterned to define a resist mask. The amorphous carbon doped layer is etched to define a hardmask, the resist mask is stripped, and the metal layer not covered by the hardmask is etched to form a metal line for forming an interconnect.

Abstract: A method of etching a low-k dielectric layer. A substrate having a low-k dielectric layer to be etched, on which an amorphous carbon doped layer is formed over the low-k dielectric layer by plasma enhanced chemical vapor deposition (PECVD), a resist layer is formed over the amorphous carbon doped layer , and the resist layer is patterned to define a first opening thereby forming a resist mask. The amorphous carbon doped layer is etched to define a second opening, thereby forming a hardmask, the resist mask is stripped, and the low-k dielectric layer not covered by the hardmask is etched to form a third opening as a trench or via.

Abstract: A method to fabricate an interconnect structure is provided. First, an inter-metal dielectric layer is formed on a substrate. Then the inter-metal dielectric layer is etched to form a trench, and a barrier layer is formed on the trench. After, a metal layer is formed to fill in the trench over the barrier layer. Then a chemical mechanical polishing (CMP) process is performed to remove the barrier layer and the metal layer on the inter-metal dielectric layer. Finally, a conductive sealing layer is formed to cover the metal layer.