Patents by Inventor Ching Fang

Ching Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250251638
    Abstract: A front-light glass display module includes an image display unit, an adhesive layer, and a front-light unit. The adhesive layer is stacked on one side of the image display unit, and is made of an optical clear adhesive and a buffer material. The front-light unit is installed on the adhesive layer and remote to the image display unit. The front-light unit has a glass sheet and a light-guiding structure. The glass sheet is stacked on the adhesive layer. The light-guiding structure is installed on at least one side of the glass sheet that faces or faces away from the adhesive layer. The light-guiding structure guides and transmits light to the image display unit uniformly. The front-light unit uses the high-strength glass sheet to eliminate the need of a protection layer for the conventionally used plastic structure, thereby reducing the overall thickness and weight while saving manufacturing costs.
    Type: Application
    Filed: August 20, 2024
    Publication date: August 7, 2025
    Applicant: CHENFENG OPTRONICS CORPORATION
    Inventors: CHING-FANG WONG, YU-WEI LIU, WEI-LUN ZENG, BANG-JIN YOU
  • Publication number: 20250216764
    Abstract: An EUV lithography mask including a substrate, a patterned absorber layer including an alloy of rhodium. In some embodiments, the alloy of rhodium includes a group 5, group 6, group 9, group 10, or group 11 transition metal having a specific EUV refractive index and a specific EUV extinction coefficient. The disclosed EUV lithography masks reduce undesirable mask 3D effects.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 3, 2025
    Inventors: Pei-Cheng HSU, Sih-Wei CHANG, Hsuan-I WANG, Yu-Hsiang KAO, Ching-Fang YU, Hsin-Chang LEE
  • Patent number: 12314869
    Abstract: An electronic device and a method of filtering dispatching rules for a workstation are provided. The method includes the following. A dispatch rule set including a first dispatching rule and a first test data set are obtained. An initial individual is generated according to the dispatch rule set based on a genetic algorithm. A first individual is generated according to the first test data set and the initial individual based on the genetic algorithm, and the first individual includes a first dispatching rule sequence corresponding to a first workstation, and the first dispatching rule sequence includes a first dispatching rule. A first score corresponding to the first dispatching rule is calculated according to a first order of the first dispatching rule in the first dispatching rule sequence, and the dispatching rule set is updated according to the first score. The dispatching rule set that is updated is output.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: May 27, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Tung-Han Wu, Ching-Fang Shao
  • Publication number: 20250123552
    Abstract: An extreme ultraviolet (EUV) mask and method of forming an EUV mask are provided. The method includes forming a mask layer on a semiconductor wafer, generating extreme ultraviolet (EUV) light by a lithography exposure system, forming patterned EUV light by patterning the EUV light by a mask including an absorber having extinction coefficient at an EUV wavelength that exceeds extinction coefficients of TaBN and TaN at the EUV wavelength, and exposing the mask layer by the patterned EUV light.
    Type: Application
    Filed: April 5, 2024
    Publication date: April 17, 2025
    Inventors: Pei-Cheng HSU, Hsuan-I WANG, Ping-Hsun LIN, Ching-Fang YU, Chia-Jen CHEN, Hsin-Chang LEE
  • Patent number: 12272691
    Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chang-Fen Hu, Shao-Yu Li, Kuo-Ji Chen, Chih-Peng Lin, Chuei-Tang Wang, Ching-Fang Chen
  • Patent number: 12265322
    Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Hsun Lin, Pei-Cheng Hsu, Ching-Fang Yu, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 12253558
    Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fang Chen, Hsiang-Tai Lu, Chih-Hsien Lin
  • Publication number: 20250087580
    Abstract: A method of forming a three dimensional integrated circuit (3DIC) structure includes forming a first inter-layer via which connects at a location of a first device layer, wherein the first inter-layer via has a footprint that is at least one factor of ten smaller than a footprint of a first circuit region. The method further includes forming a first conductive segment in a second device layer, different from the first device layer, wherein the first conductive segment electrically connects to the first inter-layer via.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Inventors: Yi-Lin CHUANG, Ching-Fang CHEN, Jia-Jye SHEN
  • Publication number: 20250074815
    Abstract: A glass display cover with realistic haptic texture and a manufacturing method thereof are disclosed. The glass display cover is for being installed at one side of a display module. The glass display cover includes a glass substrate, a pattern layer, a pattern-highlighting layer, and a textured layer. The glass substrate is installed at the side of the display module. The pattern layer is formed by color layers stacked on the glass substrate. The pattern-highlighting layer is on a side of the pattern layer facing away from the glass substrate. The pattern-highlighting layer is made of a mixture of a white ink and a diluent. The textured layer is formed at a revere side of the glass substrate. The textured layer is made of a solvent material mixed with particles. The manufacturing method includes forming the layers. The textured layer endows the glass display cover with added qualitative value.
    Type: Application
    Filed: August 12, 2024
    Publication date: March 6, 2025
    Applicant: CHENFENG OPTRONICS CORPORATION
    Inventors: CHING-FANG WONG, YU-WEI LIU, WEI-LUN ZENG, BANG-JIN YOU
  • Publication number: 20250068811
    Abstract: An integrated circuit design implementation system includes a synthesis tool configured to: receive a behavioral description of each of a plurality of first components; generate first netlists based on the behavioral descriptions of the first components; receive connection information of a plurality of second components, wherein the connection information comprises physical arrangement and connectivity among the first components and the second components; generate a plurality of third components, wherein each of the third components operatively corresponds to an interface between a pair of one of the first components and one of the second components; and transform the first netlists to a second netlist based on first vertices, second vertices, third vertices, and edges. The first vertices correspond to the first components, respectively, the second vertices correspond to the second components, respectively, and the third vertices correspond to the third components, respectively.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Chen, Ang-Chih Hsieh, Wei-Heng Lo, Heng-Yi Lin, Chih-Wei Chang
  • Publication number: 20250060660
    Abstract: A method includes: generating a designed mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask metrology apparatus including a light source having a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern while the mask is under the alignment.
    Type: Application
    Filed: January 3, 2024
    Publication date: February 20, 2025
    Inventors: Cheng-Yeh LEE, Ching-Fang YU, Hsueh-Wei HUANG, Yen-Cheng HO, Wei-Cheng LIN, Hsin-Yi YIN
  • Patent number: 12154851
    Abstract: A method (of forming a three dimensional integrated circuit (3DIC) structure) includes: forming an interconnection layer including forming a first inter-layer via which connects at a first predetermined location to a first circuit region of a first device layer and which has a footprint that is at least one factor of ten smaller than a footprint of the first circuit region; and forming a first conductive segment in a first metallization layer of a second device layer so as to align with and thereby connect to the first inter-layer via.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen
  • Publication number: 20240311638
    Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.
    Type: Application
    Filed: December 28, 2023
    Publication date: September 19, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Nien-Tzu Chou, Yu-Yu Lin, Ching-Fang Lu, Jian-Hao Li, Ting-Hsuan Chen, Cheng-Tai Chen
  • Patent number: 12053944
    Abstract: A dyeing method for functional contact lenses includes the following steps: providing a dry lens body, including hydrogel with 0-90% water content, silicone hydrogel with 0-90% water content, or a combination thereof; preparing an amphoteric polymethyl ether prepolymer, combining the amphoteric polymethyl ether prepolymer with a hydrophilic monomer to form a masking ring material, and attaching the masking ring material to an inner surface of the dry lens body to form a masking ring layer; dropping a colorant onto the inner surface, making the masking ring layer surround the colorant, irradiating the colorant with an ultraviolet light and then heating and fixing the colorant to form a dyed layer on the inner surface; and placing the dry lens body in water to hydrate and removing the masking ring layer to obtain a wet lens body.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: August 6, 2024
    Assignee: VIZIONFOCUS INC.
    Inventors: Wen-Ching Lin, Ching-Fang Lee, Chi-Ching Chen, Hsiao-Chun Lin
  • Patent number: 12024457
    Abstract: The present invention provides a flexible glass and manufacturing method thereof. The flexible glass includes a first straight part and a second straight part on two opposite ends thereof, a recess formed between the first straight part and the second straight part, and a pre-bent curve connection part disposed corresponding to the recess. The first straight part and the second straight part are not arranged on the same plane. The flexible glass has a first lateral side and a second lateral side, and the recess sinks from the first lateral side toward the second lateral side. Therefore, the flexible glass is provided with a greater bendability.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: July 2, 2024
    Assignee: CHENFENG OPTRONICS CORPORATION
    Inventors: Ching-Fang Wong, Yu-Wei Liu, Wei-Lun Zeng, Kuan-Hua Liao
  • Publication number: 20240157801
    Abstract: A method for estimating a flight time of a hydrogen fuel cell UAV (unmanned aerial vehicle) includes multiple steps performed by a controller: obtaining an internal pressure of a hydrogen tank by a pressure sensor installed on the hydrogen tank, calculating a remaining hydrogen volume according to the internal pressure and a capacity of the hydrogen tank, obtaining a reaction current value of the fuel cell, calculating a first hydrogen consumption rate according to the reaction current value, the number of a set of membrane electrodes connected in series and a Faraday constant, obtaining a second hydrogen consumption rate of a purge operation of an anode of the full cell; obtaining a hydrogen leakage rate of a stack of the fuel cell, and calculating the flight time according to the remaining hydrogen volume, the first hydrogen consumption rate, the second hydrogen consumption rate and the hydrogen leakage rate.
    Type: Application
    Filed: May 18, 2023
    Publication date: May 16, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ching-Jung LIU, Yuh-Fwu CHOU, Ku-Yen KANG, Yin-Wen TSAI, Ching-Fang HO, Cheng-Hsien YU
  • Patent number: 11959101
    Abstract: A cell activation reactor and a cell activation method are provided. The cell activation reactor includes a body, a rotating part, an upper cover, a microporous film, and multiple baffles. The body has an accommodating space, which is suitable for accommodating multiple cells and multiple magnetic beads. The rotating part is disposed in the accommodating space and includes multiple impellers. The microporous film is disposed in the accommodating space and covers multiple holes of the accommodating space. The baffles are disposed in the body. When the rotating part is driven to rotate, the interaction between the baffles and the impellers separates the cells and the magnetic beads.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: April 16, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Ting-Hsuan Chen, Kuo-Hsing Wen, Ya-Hui Chiu, Nien-Tzu Chou, Ching-Fang Lu, Cheng-Tai Chen, Ting-Shuo Chen, Pei-Shin Jiang
  • Publication number: 20240109803
    Abstract: The present invention provides a flexible glass and manufacturing method thereof. The flexible glass includes a first straight part and a second straight part on two opposite ends thereof, a recess formed between the first straight part and the second straight part, and a pre-bent curve connection part disposed corresponding to the recess. The first straight part and the second straight part are not arranged on the same plane. The flexible glass has a first lateral side and a second lateral side, and the recess sinks from the first lateral side toward the second lateral side. Therefore, the flexible glass is provided with a greater bendability.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: CHENFENG OPTRONICS CORPORATION
    Inventors: CHING-FANG WONG, YU-WEI LIU, WEI-LUN ZENG, KUAN-HUA LIAO
  • Publication number: 20240102090
    Abstract: The present disclosure provides a methodology for multimodal profiling of extracellular vesicles at single-particle resolution, including technique, workflow, and analytical algorithm.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 28, 2024
    Inventors: Yuchao CHEN, Ching-Fang CHANG
  • Patent number: D1058339
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: January 21, 2025
    Inventors: Yu-Chun Chan, Ching-Fang Chang