Patents by Inventor Ching-Fang Huang
Ching-Fang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9293378Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: GrantFiled: July 6, 2015Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
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Publication number: 20160005660Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: ApplicationFiled: July 6, 2015Publication date: January 7, 2016Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
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Patent number: 9093566Abstract: Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: GrantFiled: July 25, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
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Publication number: 20150162334Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: ApplicationFiled: February 18, 2015Publication date: June 11, 2015Inventors: Jon-Hsu HO, Chih-Ching WANG, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Chih-Chieh YEH, Ken-Ichi GOTO, Zhiqiang WU
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Patent number: 8987824Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: GrantFiled: November 22, 2011Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Chih-Chieh Yeh, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20150079752Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: ApplicationFiled: November 13, 2014Publication date: March 19, 2015Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Patent number: 8981479Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: GrantFiled: December 17, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Patent number: 8890207Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: GrantFiled: December 22, 2011Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Publication number: 20140183641Abstract: Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: ApplicationFiled: July 25, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
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Patent number: 8765533Abstract: A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin.Type: GrantFiled: December 4, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsing Hsieh, Zhiqiang Wu, Ching-Fang Huang, Jon-Hsu Ho
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Publication number: 20140103438Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching WANG, Jon-Hsu HO, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Ken-Ichi GOTO, Zhiqiang WU
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Patent number: 8623716Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: GrantFiled: November 3, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20130126981Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jon-Hsu HO, Chih-Ching WANG, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Chih-Chieh YEH, Ken-Ichi GOTO, Zhiqiang WU
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Publication number: 20130113042Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20130056795Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: ApplicationFiled: December 22, 2011Publication date: March 7, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Patent number: 8009479Abstract: A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.Type: GrantFiled: November 12, 2009Date of Patent: August 30, 2011Assignee: National Taiwan UniversityInventors: Yen-Ting Chen, Ching-Fang Huang, Hung-Chang Sun, Chee Wee Liu
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Publication number: 20110032765Abstract: A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.Type: ApplicationFiled: November 12, 2009Publication date: February 10, 2011Applicant: National Taiwan UniversityInventors: Yen-Ting Chen, Ching-Fang Huang, Hung-Chang Sun, Chee Wee Liu
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Publication number: 20080145979Abstract: A method for changing a characteristic of a thin film transistor (TFT) is provided. The method comprises the steps of (1) providing a substrate; (2) forming the TFT having a channel on the substrate; (3) providing a pressure source; and (4) causing the pressure source to form a strain on the channel. The method for changing the characteristic of the TFT can further raise the operational speed thereof.Type: ApplicationFiled: December 6, 2007Publication date: June 19, 2008Applicant: NATIONAL TAIWAN UNIVERSITYInventors: Ching-Fang HUANG, Chee-Zxiang LIU, Chee-Wee LIU
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Publication number: 20050118758Abstract: A method for arranging a layout of a CMOS (Complementary Metal-Oxide Semiconductor) device is provided. The current direction of the N-type MOS device is perpendicular to the P-type MOS device. The stress along one direction can be applied on both types of MOS devices to enhance the drain current and the operation speed of both devices for CMOS circuit.Type: ApplicationFiled: November 5, 2004Publication date: June 2, 2005Inventors: Feng Yuan, Ching-Fang Huang, Cheewee Liu