Abstract: A cutting machine for cutting a window covering includes a machine base and a cutting device provided on the machined base. The machine base includes a sustaining face for putting the window covering thereon. The cutting device includes a frame provided on the machine base, a cutter, a movable block, a stopping block and a connecting bar. The control bar is pivoted on the frame and controllable to pivotally swing and drive the cutter to move up and down. The movable block is moved along with the cutter to drive the connecting bar to pivotally swing relative to the frame. The stopping block is adapted to abut against one end of the window covering to be cut and is further driven by the connecting bar to reciprocate along the machine base.

Abstract: A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.

Abstract: A light source module including a light guide plate, a light source, and a quantum dot layer is provided. The light guide plate has a light emitting surface, a bottom surface, and a light incidence surface, wherein the bottom surface is opposite to the light emitting surface, and the light incidence surface connects the bottom surface and the light emitting surface. The light source is disposed beside the light incidence surface. The quantum dot layer is disposed on at least one of the light emitting surface and the bottom surface.

Abstract: An optical transmittance adjustment device including a light guide plate and an optical transmittance adjustment film is provided. The light guide plate has a first surface and a second surface, wherein the second surface is opposite to the first surface and has a plurality of light scattering microstructures. The optical transmittance adjustment film is located at a side of the light guide plate, and the light scattering microstructures are located between the optical transmittance adjustment film and the light guide plate.

Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.

Abstract: A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.

Abstract: An autonomous mobile robot, adapted to move on a surface according to a moving datum plane, is provided. The autonomous mobile robot comprising; a first distance sensor configured to detect a first detecting distance between the first distance sensor and the surface along a first axial direction; a second distance sensor configured to detect a second detecting distance between the second distance sensor to the surface along a second axial direction; and a control unit configured to control the autonomous mobile robot to move in a speed limited mode when the first detecting distance is within a first distance range, and configured to control the autonomous mobile robot to stop moving when the second detecting distance is larger than a second pre-determined distance. A mobile control method is also provided.

Abstract: A support structure located at a bottom of a ball grid array (BGA) is provided. The support structure includes a printed circuit board (PCB) having first positioning pin holes, an interface plate having second positioning pin holes which correspond to the first positioning pin holes arranged on the PCB, a support film arranged on the PCB and having support portions, and positioning components penetrating the first positioning pin holes and the second positioning pin holes corresponding to the first positioning pin holes to assemble the support film on the PCB and the interface plate.

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

Abstract: A light guide plate including a light guide main body and an index matching layer is provided. The light guide main body has a light-emitting surface and a bottom surface opposite to the light-emitting surface. The index matching layer is disposed adjacent to the bottom surface, wherein a refractive index of the light guide main body is n1, and a refractive index of the index matching layer is n2. 1.07*n2?n1?1.7*n2, and 0.1?(n1?n2)?0.7. A thickness of the index matching layer is larger than 500 nm. A backlight module and a display apparatus are also provided.

Abstract: A circuit test structure includes: a chip including a conductive line which traces a perimeter of the chip; an interposer electrically connected to the chip; and a Kelvin test structure including: at least three electrical connections to the conductive line; and a testing site. The Kelvin test structure is configured to electrically connect the testing site to the conductive line.

Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. Such a method includes: placing a power supply rail pattern in a first device layer of the IC; bundling, for purposes of placement, a voltage level shifter and one or more inter-layer vias together as an integral unit; and placing the integral unit in the first device layer of the IC design such that one or more metal line patterns in the voltage level shifter are located parallel to albeit without overlapping the power supply rail pattern. The placing the integral unit forms a direct electrical connection channel between the voltage level shifter and a metal pattern in a second device layer of the IC design. At least one of the placing operations is performed using a layout generating machine.

Abstract: The bar code classification system includes a storage unit, a bar code generating unit, a bar code printing apparatus, and a processing unit. The storage unit is adapted for storing a commodity information of each of plural commodities. The bar code generating unit is adapted for generating a plurality of bar code patterns. The bar code printing apparatus is connected to the bar code generating unit and is adapted for printing the bar code patterns into bar codes. Each bar code is not directed to any specific one of the commodities. The bar codes are shown on the commodities. The processing unit inputs a bar code information of each of the commodities having the bar codes into the storage unit, and links each of the bar code informations to the commodity information of corresponding commodity. Thus, the bar codes can be used more flexibly.

Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. In an embodiment, the FinFET diode further has metal contacts formed upon the semiconductor strips. In another embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.

Abstract: Determining RAN performance outlier information is disclosed. In an aspect, RAN data for a current condition can be analyzed in view of historical RAN data to determine if the current condition in atypical and represents an outlier condition. In an aspect, historically similar environments between the historical and current RAN data can allow the analysis to have increased relevance. The disclosure can employ a binary array to facilitate determining performance outlier information. In an aspect, the present disclosure can be performed in a distributed computing environment and is scalable to manage large data volumes. Performance outlier information can be employed in alerts, scheduling repair, planning hardware or software upgrades, tracking rollout of new features, etc.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.

Abstract: A cutting machine for window coverings is disclosed, which includes a worktable, a first cutting device, and a caliper. An abutting member and at least one series of extending graduation marks are provided on a table surface of the worktable. The caliper includes at least one internal gauge point and at least one external gauge point. By making the internal gauge point or the external gauge point of the caliper point at a scale value of the series of extending graduation marks which matches a height of a window opening, and by cutting the slats, the resultant slats are adapted to be installed to the window opening. In addition, a distance between a surface of the first cutting device which bears the slats and the table surface of the worktable is short, which makes the stacked slats can be cut in a substantially horizontal way.

Abstract: A light emitting diode (LED) packaging structure including a metal pad, an electric static discharge (ESD) protection element and an LED chip is provided. The metal pad has a first pad portion having a first top surface with a first concave configured thereon and a second pad portion having a second top surface with a second concave configured thereon. The ESD protection element has two first electrode portions respectively configured in the first concave and the second concave. The LED chip is located above the ESD protection element and has two second electrode portions respectively configured on the first top surface and the second top surface. A frame and a light emitting device having the frame that both include the above LED packaging structure are described herein. A light emitting device having an omni-directional light emitting effect is also described and includes the above LED packaging structure.