Abstract: A metal mask structure includes a plate and slits formed thereon. Each slit extends along a first direction and includes a first opening and a second opening formed on front and back surfaces, respectively, and communicating with each other to penetrate through the plate. A first longitudinal length of the first opening is smaller than a second longitudinal length of the second opening. The first opening has opposite first and second ends; the second opening has corresponding third and fourth ends. A first distance between the first end and the third end projected on the front surface parallel to the first direction is less than or equal to 200 ?m. In a direction perpendicular to the first direction, a maximum width of the second opening is an extended width, and a width of the third end is a second end width less than or equal to the extended width.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: The present invention discloses a method of producing a medical implant adopting additive manufacturing including: distributing magnesium-zinc-zirconium alloy powder on a substrate to form a powder layer; generating a high-energy beam within a specific power range and directing the high-energy beam to the powder layer through a probe to sinter a region of the powder layer; distributing the plurality of magnesium-zinc-zirconium alloy powder on the sintered region of the powder layer; and repeating above steps until the medical implant is formed.

Abstract: An instrument sterilization monitoring system and an instrument sterilization monitoring method are provided. The instrument sterilization monitoring system includes a server, a sterilization device, and a mobile device. An image capturing module of the mobile device is used to capture image information of a first sterilization device indication device in the sterilization device, image information of a first sterilization device indication label, image information of a second instrument indication device, and image information of a second instrument indication label which are disposed outside an instrument package. The image information is uploaded to the server. The server determines, according to the image information, whether or not the instrument package meets a sterilization standard.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.

Abstract: An interactive projection system including a projector and a touch interactive light source device is provided. The projector includes a projection optical engine, a camera module, and a control module. The touch interactive light source device includes at least one infrared light source module and a wireless signal transmission module. The control module is electrically connected to the projection optical engine and the camera module, and controls the touch interactive light source device through the wireless signal transmission module, so that the touch interactive light source device is placed in a recommended installation position and the interactive projection system is in an interactive mode. An operation method of the interactive projection system is also provided.

Abstract: A method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A package structure, including a circuit board, multiple circuit structure layers, at least one bridge structure, and at least one supporting structure, is provided. The circuit structure layer is disposed on the circuit board. The bridge structure is connected between the two adjacent circuit structure layers. The supporting structure is located between the two adjacent circuit structure layers, and the supporting structure has a first end and a second end opposite to each other and respectively connecting the bridge structure and the circuit board.

Abstract: The present invention relates to method for producing LED by one step film lamination. The method comprises: laminating two or more LEDs with two or more colored phosphor films by one step film lamination; wherein each of the colored phosphor film comprises each other different colored phosphor composition which has a Maximum tan ?; and the difference of each Maximum tan ? varies within a range of 0-30%. In the present invention, the method for producing a LED may greatly improve production efficiency (i.e., dual and multi-color LEDs in one step) and lower cost of ownership. Further, it may improve uniformity of phosphor dispersion, thereby improve color quality of LEDs.

Abstract: An electronic device is provided. The electronic device includes a first carrier having a first surface, an interposer disposed over the first surface of the first carrier, wherein the interposer has a first thickness and a second thickness in a direction substantially perpendicular to the first surface of the first carrier; and a plurality of electrical connections between the first carrier and the interposer and configured to compensate a difference between the first thickness and the second thickness of the interposer.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

Abstract: Systems and methods for implementing array cameras configured to perform super-resolution processing to generate higher resolution super-resolved images using a plurality of captured images and lens stack arrays that can be utilized in array cameras are disclosed. An imaging device in accordance with one embodiment of the invention includes at least one imager array, and each imager in the array comprises a plurality of light sensing elements and a lens stack including at least one lens surface, where the lens stack is configured to form an image on the light sensing elements, control circuitry configured to capture images formed on the light sensing elements of each of the imagers, and a super-resolution processing module configured to generate at least one higher resolution super-resolved image using a plurality of the captured images.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.