Abstract: An optical switch module includes a housing, at least two first collimators, at least two second collimators, a relay, and plural prisms. The housing has an accommodating space, a first sidewall, and a second sidewall. The first collimators are located on the first sidewall. Each of the first collimators connects even number of first fibers. The second collimators are located on the second sidewall. Each of the second collimators connects even number of second fibers. The second collimators are respectively aligned with the first collimators. The relay is located in the accommodating space and has a rotation support. The prisms are located on the rotation support and respectively between the first and second collimators. The rotation support is configured to enable at least one of the prisms to be in light transmission paths between the first fibers and the second fibers.

Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Abstract: A semiconductor device includes a dielectric structure, a conductive structure disposed in the dielectric structure, a first dielectric feature disposed over the dielectric structure, a conductive element disposed in the first dielectric feature and connected to the conductive structure, and a barrier feature disposed around the conductive element and disposed outside of the conductive structure.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers, two epitaxial structures, a conductive structure, a via, and a graphene barrier. The channel layers and the epitaxial structures are disposed over the substrate. The channel layers are connected between the epitaxial structures. The conductive structure is disposed on the substrate opposite to the epitaxial structures. The via is connected between one of the epitaxial structure and the conductive structure. The graphene barrier surrounds the via.

Abstract: A semiconductor device includes a substrate and an interconnect layer disposed on the substrate. The interconnect layer includes a dielectric layer and an interconnect extending through the dielectric layer. The interconnect includes a bulk metal region and a single barrier/liner layer, which serves as both a barrier layer and a liner layer and which is disposed to separate the bulk metal region from the dielectric layer.

Abstract: An interconnection structure includes a conductive feature disposed in a first dielectric material, a first etch stop layer disposed over the first dielectric material, a second dielectric material disposed on the first etch stop layer, a conductive via extending through the second dielectric material and the first etch stop layer and in contact with at least a portion of the conductive feature, a first barrier layer disposed between the second dielectric material and the conductive via, a first liner disposed between and in contact with the first barrier layer and the conductive via, a third dielectric material disposed over the second dielectric material, a conductive line disposed in the third dielectric material and in direct contact with the conductive via, a second barrier layer disposed on the second dielectric material and in contact with the first barrier layer and the conductive line, and a second liner disposed between and in contact with the second barrier layer and the conductive line, wherein th

Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Abstract: A semiconductor device includes an interconnect structure embedded in a first metallization layer comprising a dielectric material. The interconnect structure includes a first metal material. The semiconductor device includes a first liner structure embedded in the first metallization layer. The first liner structure is extended along one or more boundaries of the interconnect structure in the first metallization layer. The first liner structure includes a second metal material reacted with one or more dopants, the second metal material being different from the first metal material.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer.

Abstract: A method for manufacturing a semiconductor comprises: providing a substrate; forming an opening in a dielectric layer disposed over the substrate; providing a target with a first type atoms; ionizing the first type atoms provided from the target; providing a bias to the substrate for controlling the moving paths of the ionized first type atoms thereby directing the ionized first type atoms in the opening; and forming a first conductive structure from bottom of the opening with the ionized first type atoms under a pre-determined frequency and a pre-determined pressure.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Abstract: A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer.

Abstract: A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer.

Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an ?-phase inducing metal layer is introduced on a first Ta barrier layer of ? phase to induce the subsequent deposition of Ta thereon into the formation of an ?-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of ? phase has a lower Rc than that of the ?-phase Ta barrier layer.