Patents by Inventor Ching-Hao Chang
Ching-Hao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145379Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.Type: ApplicationFiled: February 23, 2023Publication date: May 2, 2024Inventors: Yen-Kun Lai, Wei-Hsiang Tu, Ching-Ho Cheng, Cheng-Nan Lin, Chiang-Jui Chu, Chien Hao Hsu, Kuo-Chin Chang, Mirng-Ji Lii
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Publication number: 20240136291Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.Type: ApplicationFiled: January 12, 2023Publication date: April 25, 2024Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
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Patent number: 11967591Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.Type: GrantFiled: August 6, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
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Patent number: 11942451Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
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Publication number: 20240096701Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.Type: ApplicationFiled: May 17, 2023Publication date: March 21, 2024Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Ching-Wei TSAI, Shang-Wen CHANG, Yi-Hsun CHIU, Chih-Hao WANG
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Patent number: 11935757Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 11358868Abstract: The present invention relates to a device comprising physical properties controlled by a microstructure and a method of manufacturing the same. The present invention discloses a base layer having a patterned surface; and a two-dimensional structure layer formed on the patterned surface of the base layer, the two-dimensional structure layer extending on and in compliance to topography of the patterned surface of the base layer, such that change of physical properties of the two-dimensional structure layer conforms to the stress generated along the topography.Type: GrantFiled: December 18, 2019Date of Patent: June 14, 2022Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Tse-Ming Chen, Sheng-Chin Ho, Yu-Chiang Hsieh, Ching-Hao Chang
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Publication number: 20210009423Abstract: The present invention relates to a device comprising physical properties controlled by a microstructure and a method of manufacturing the same. The present invention discloses a base layer having a patterned surface; and a two-dimensional structure layer formed on the patterned surface of the base layer, the two-dimensional structure layer extending on and in compliance to topography of the patterned surface of the base layer, such that change of physical properties of the two-dimensional structure layer conforms to the stress generated along the topography.Type: ApplicationFiled: December 18, 2019Publication date: January 14, 2021Inventors: Tse-Ming CHEN, Sheng-Chin HO, Yu-Chiang HSIEH, Ching-Hao CHANG
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Patent number: 8801224Abstract: The present invention provides an LED illumination device including a base, at least one flexible circuit board and a plurality of LEDs. The at least one flexible circuit board is used for covering the base. The LEDs are mounted on the flexible circuit board. The present invention utilizes a flexible circuit board that can conform to the base having a 360 degree curved surface and a 3D solid structure to efficiently change the viewing angle of the LEDs so as to provide 360 degree viewing angle. Furthermore, a single flexible circuit board can be utilized to cover the base to provide a 360 degree viewing angle. Therefore, the LED illumination device of the present invention can reduce manufacturing cost and simplify the manufacturing process.Type: GrantFiled: June 9, 2011Date of Patent: August 12, 2014Assignee: Parlux Optoelectronics Co., Ltd.Inventors: Tang-Chieh Huang, Yu-Tang Yen, Ching-Hao Chang, Bing-You Weng, Sunao Hsu, Yao-Wen Liu
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Publication number: 20120106153Abstract: The present invention provides an LED illumination device including a base, at least one flexible circuit board and a plurality of LEDs. The at least one flexible circuit board is used for covering the base. The LEDs are mounted on the flexible circuit board. The present invention utilizes a flexible circuit board that can conform to the base having a 360 degree curved surface and a 3D solid structure to efficiently change the viewing angle of the LEDs so as to provide 360 degree viewing angle. Furthermore, a single flexible circuit board can be utilized to cover the base to provide a 360 degree viewing angle. Therefore, the LED illumination device of the present invention can reduce manufacturing cost and simplify the manufacturing process.Type: ApplicationFiled: June 9, 2011Publication date: May 3, 2012Applicant: PARLUX OPTOELECTRONICS CO, LTD.Inventors: TANG-CHIEH HUANG, Yu-Tang Yen, Ching-Hao Chang, Bing-You Weng, Sunao Hsu, Yao-Wen Liu