Abstract: A micro light-emitting diode display device and a micro light-emitting diode structure. The micro light-emitting diode display device includes a circuit substrate and a plurality of display pixels, the display pixels are arranged on the circuit substrate and are electrically connected with the circuit substrate individually. Each display pixel includes a plurality of series-connection structures, and the light wavelengths of the series-connection structures are different. Each series-connection structure includes at least two micro light-emitting elements, and the light wavelengths of the at least two micro light-emitting elements are within a wavelength range of one color light. The circuit substrate provides a driving voltage to drive the series-connection structures of each display pixel.

Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: A reactive UV absorber suitable for polyurethane is provided. The reactive UV absorber is a compound of formula 1: wherein R1 is H or Cl.

Abstract: A reactive UV absorber suitable for polyurethane is provided. The reactive UV absorber is a compound of formula 1: wherein R1 is H or Cl.