Abstract: A circuit includes a capacitor and a memory element. The capacitor includes a first conductive layer, a first terminal, and a second terminal. The first conductive layer includes a first plurality of bars extending along a first direction and parallel to one another, where two adjacent bars of the first plurality of bars have a first capacitance therebetween. The first terminal is coupled with a first bar of the two adjacent bars, and the second terminal is coupled with a second bar of the two adjacent bars. The memory element has an input coupled with the first terminal and an output coupled with the second terminal. The capacitor is configured to inhibit changing a logic state at the input of the memory element.

Abstract: A circuit includes a capacitor and a memory element. The capacitor includes a first conductive layer, a first terminal, and a second terminal. The first conductive layer includes a first plurality of bars extending along a first direction and parallel to one another, where two adjacent bars of the first plurality of bars have a first capacitance therebetween. The first terminal is coupled with a first bar of the two adjacent bars, and the second terminal is coupled with a second bar of the two adjacent bars. The memory element has an input coupled with the first terminal and an output coupled with the second terminal. The capacitor is configured to inhibit changing a logic state at the input of the memory element.

Abstract: Some embodiments are related to a mesh capacitor, which improves the SER FIT rate. In an embodiment, the capacitor is connected between an input and an output of a latch in a flip-flop, making the flip-flop harder to flip due to radiation (e.g., from neutrons and/or alpha particles). In some embodiments, the capacitor is built directly vertically on top of the flip-flop, saving chip layout areas.

Abstract: Some embodiments are related to a mesh capacitor, which improves the SER FIT rate. In an embodiment, the capacitor is connected between an input and an output of a latch in a flip-flop, making the flip-flop harder to flip due to radiation (e.g., from neutrons and/or alpha particles). In some embodiments, the capacitor is built directly vertically on top of the flip-flop, saving chip layout areas.

Abstract: An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell.

Abstract: An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell.

Abstract: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Abstract: Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an M1 wire formed outside the filler cell while the second voltage supply wire is an M2 wire formed inside the filler cell.

Abstract: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Abstract: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Abstract: Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an M1 wire formed outside the filler cell while the second voltage supply wire is an M2 wire formed inside the filler cell.

Abstract: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Abstract: Standard cell layout efficiency is improved by utilization of a MOS interconnect that minimizes features and geometries requiring compliance with space intensive design rules. Source diffusion regions of MOS structures have a substantially constant width extension extending toward a substrate pick-up diffusion and shares a common silicidation therewith to effect an ohmic contact thereto.

Abstract: Standard cell layout efficiency is improved by utilization of a MOS interconnect that minimizes features and geometries requiring compliance with space intensive design rules. Source diffusion regions of MOS structures have a substantially constant width extension extending toward a substrate pick-up diffusion and shares a common silicidation therewith to effect an ohmic contact thereto.

Abstract: A base cell, having four sites, for use in a gate array retains the same design rules as a prior art base cell, but the area of the base cell has been reduced. The reduction in the size of the base cell is the result of arranging all transistor pairs to be fabricated over a common moat regions, thereby eliminating areas previously used for moat-to-moat spacing. In addition, at least one moat region is configured to permit a conducting path passing nearby to observe the design rules without appreciable. Components forming the base cell have been rearranged to permit the D-type flip-flop circuit to be implemented using three of the base cell sites instead of the four base cell sites required by the prior art. This component rearrangement is useful for other circuits implemented by the base cell as well.

Abstract: A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites.

Abstract: A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor gates in the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites.

Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and a predetermined plurality of the column locations. Elongate gate conductors (584-602) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). Selected ones (e.g. 514, 544) of the transistors are merged in a row direction if the logic does not require them to be isolated from one another. A plurality of elongate second conductors (222) interconnect to selected ones of the sources or drains of the transistors (224). Non-Boolean portions of the logic circuitry are formed in an adjacent tile section (214) in the semiconductor layer separate from the logic array (212).

Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and one of the column locations. Elongate gate conductors (e.g., G, H, I) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). A plurality of elongate second conductors (222) connect to selected ones of the sources or drains of the transistors (224) and to non-Boolean portions of the dynamic logic circuits. The non-Boolean portions are formed in an adjacent tile section (214) in the semi-conductor layer separate from the logic array (212).

Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and a predetermined plurality of the column locations. Elongate gate conductors (584-602) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). Selected ones (e.g. 514, 544) of the transistors are merged in a row direction if the logic does not require them to be isolated from one another. A plurality of elongate second conductors (222) interconnect to selected ones of the sources or drains of the transistors (224). Non-Boolean portions of the logic circuitry are formed in an adjacent tile section (214) in the semiconductor layer separate from the logic array (212).