Abstract: A three-dimensional integrated circuit stack comprises a first integrated circuit structure, a second integrated circuit structure bonding to the first integrated circuit structure, and a redistribution structure. The first integrated circuit structure comprises a first semiconductor device, a first buffer structure, a first interconnect structure, a first conductive via, and a first through via. The first semiconductor device is located between the first buffer structure and the first interconnect structure. The first conductive via is extending through the first buffer structure and in contact with the first semiconductor device. The first through via is extending from the first buffer structure to the first interconnect structure. The redistribution structure is disposed on the first buffer structure, electrically connected to the first semiconductor device through the first conductive via, and electrically connected to the first interconnect structure through the first through via.

Abstract: A system for expense management including an expense management apparatus. The expense management apparatus configured to receive, from a client device, at least one parameter associated with an event, construct at least one query based on the at least one parameter, transmit the at least one query to a database, receive, from the database, responsive data responding to the at least one query, construct a benchmark, using a processing arrangement, associated with the at least one parameter, and transmit the benchmark to the client device.

Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.

Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Abstract: A spring lock for a skate wheel includes a housing including opposite first and second holes, and a third hole; a pin through the first and second holes and including first and second grooves; a button on the third hole; a back plate on a back of the housing; a first biasing member secured to the back plate; a stop member secured to the first groove; a sliding member having one end urging against the first biasing member and the other end contacting the button to slidably dispose on the second groove, the sliding member including small and large holes; and a second biasing member on the pin and having one end urging against an inner surface of the housing and the other end urging against the stop member. In a locked state, the pin extends into an elongated hole of between two spokes of the wheel.

Abstract: A connector includes a substrate, a coverlay and a spring contact. The substrate has a first surface, a second surface opposite to the first surface and a conductive through hole extending between the first and second surfaces. The coverlay is disposed on the first surface and includes a first opening. The spring contact includes an anchor member, a rising member and a pin. The anchor member is disposed between the substrate and the coverlay. The rising member extends from the anchor member and through the first opening in a direction away from the substrate. A first portion of the rising member is in the first opening, and a second portion of the rising member is out of the first opening. The pin extends from the anchor member to an inside of the conductive through hole, and is electrically connected to the conductive through hole.

Abstract: An LED power supply is provided. The LED power supply adopts constant-voltage/constant-current control, supplies power to an LED device, and includes an isolated DC-DC conversion circuit having primary and secondary sides and a control module. The control module includes a control unit, a feedback circuit, first and second switches and an optocoupler. The control unit is electrically connected to the primary side and controls operation of the conversion circuit. The optocoupler is configured for signal transmission with electrical isolation and includes a transmitter and a receiver electrically connected to the secondary side and the control unit respectively. When the output voltage is lower than a threshold voltage, the first switch is turned off, the second switch is turned on to trigger the optocoupler to generate a trigger signal at the receiver, and the control unit controls the isolated DC-DC conversion circuit to stop operating based on the trigger signal.

Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.

Abstract: A system for expense management including an expense management apparatus. The expense management apparatus configured to receive, from a client device, at least one parameter associated with an event, construct at least one query based on the at least one parameter, transmit the at least one query to a database, receive, from the database, responsive data responding to the at least one query, construct a benchmark, using a processing arrangement, associated with the at least one parameter, and transmit the benchmark to the client device.

Abstract: A system for software download compatibility.

Abstract: A quantum memory device includes: a waveguide configured to spatially confine paths of photons therein; a memory cell that includes a micro-ring resonator (MRR), a frequency tuner, and a quantum memory material portion, wherein the MRR includes a first segment that is parallel to a segment of the waveguide, wherein the frequency tuner is configured to modulate a photon resonance frequency in the MRR by modifying an effective refractive index within, or around, a second segment of the MRR, and wherein the quantum memory material portion includes a quantum memory material having a ground state and an excitation state that stores photons therein and located within or on a third segment of the MRR; and a control circuit configured to modulate the photon resonance wavelength in the MRR during a first step of a photon capture operation to match a predefined wavelength, and to generate captured photons in the MRR.

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate having a front-side surface and a back-side surface, and an electrical device formed over the front-side surface of a substrate. The package structure includes a dielectric layer formed below and in direct contact with the back-side surface of the substrate, and a first optical device formed in the dielectric layer. The package structure also includes a protective layer formed below or above the first optical device; and an electro-optic effect material layer formed in the protective layer.

Abstract: A package structure and a formation method are provided. The method includes forming electrical devices over a substrate and forming an interconnect structure over front sides of the electrical devices. The method also includes thinning the substrate and forming backside through vias connecting to backsides of the electrical devices. The method also includes attaching a waveguide layer over backsides of the electrical devices and forming conductive vias through the waveguide layer and electrically connected to the backside through vias.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a heat sink with an opening is disposed on an electronic component of a carrier structure, a heat dissipation material is formed in the opening, and a heat dissipation lid is disposed on the opening to cover the heat dissipation material, such that the problem of insufficient heat dissipation due to the loss of the heat dissipation material can be prevented from occurring to the electronic component.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.