Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.

Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Abstract: A projection system, a display system and monitoring methods thereof are provided. The projection system includes at least one projection device, at least one sensing device and a remote device. The at least one projection device is coupled to the at least one sensing device. The at least one sensing device senses a plurality of environmental parameters and a plurality of device output values on the at least one projection device. The remote device receives the environmental parameters and the device output values to execute state analysis for the at least one projection device, so as to generate at least one analysis result. The remote device further generates a command signal according to the at least one analysis result, and transmits the command signal to the at least one projection device. The at least one projection device executes a self-protection procedure according to the command signal.

Abstract: A projection system, a display system and monitoring methods thereof are provided. The projection system includes at least one projection device, at least one sensing device and a remote device. The at least one projection device is coupled to the at least one sensing device. The at least one sensing device senses a plurality of environmental parameters and a plurality of device output values on the at least one projection device. The remote device receives the environmental parameters and the device output values to execute state analysis for the at least one projection device, so as to generate at least one analysis result. The remote device further generates a command signal according to the at least one analysis result, and transmits the command signal to the at least one projection device. The at least one projection device executes a self-protection procedure according to the command signal.

Abstract: Disclosed are a display system, a display device and a display method of a display system. A main display device corrects display properties of a displayed image of a secondary display device according to display properties of a displayed image of the main display device, so as to adjust the displayed image of the secondary display device to have the same display properties as the displayed image of the main display device, thereby effectively improving the convenience of use of the display system and the display device.

Abstract: A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N. The first transistors have the same channel length, and the second transistors have the same channel length.

Abstract: A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N. The first transistors have the same channel length, and the second transistors have the same channel length.

Abstract: A thermal sensing system includes a circuit having a layout including standard cells arranged in rows and columns. First and second current sources provide first and second currents, respectively. The thermal sensing system includes thermal sensing units, first and second switching modules, and an analog to digital converter (ADC). Each thermal sensing unit is configured to provide a voltage drop dependent on a temperature at that thermal sensing unit. The first switching module is configured to select one of the thermal sensing units. The second switching module includes at least one switch controllable by a control signal. The at least one switch is configured to selectively couple the thermal sensing units, based on the control signal, to one of the first and second current sources, via the first switching module. The ADC is configured to convert an analog voltage, provided by the selected thermal sensing unit, to a digital value.

Abstract: An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array.

Abstract: Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.

Abstract: An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array.

Abstract: Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage.

Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.

Abstract: Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.

Abstract: Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage.

Abstract: A thermal sensing system includes a circuit having a layout including standard cells arranged in rows and columns. First and second current sources provide first and second currents, respectively. The thermal sensing system includes thermal sensing units, first and second switching modules, and an analog to digital converter (ADC). Each thermal sensing unit is configured to provide a voltage drop dependent on a temperature at that thermal sensing unit. The first switching module is configured to select one of the thermal sensing units. The second switching module includes at least one switch controllable by a control signal. The at least one switch is configured to selectively couple the thermal sensing units, based on the control signal, to one of the first and second current sources, via the first switching module. The ADC is configured to convert an analog voltage, provided by the selected thermal sensing unit, to a digital value.

Abstract: A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.