Patents by Inventor Ching-Ho Chang

Ching-Ho Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11486695
    Abstract: The present invention provides a measurement device for grinding wheel. One or more thickness measurement device is disposed slidably on a platform. A spinning device is disposed on the platform. A grinding wheel is fixed on the spinning device. The spinning shaft spins the grinding wheel. The one or more thickness measurement device measures the flatness condition of the grinding wheel. Furthermore, according to the present invention, a diameter measurement device is disposed inside the platform and measures the roundness of the outer periphery of the grinding wheel. Since the structure can be disassembled easily, the whole measurement device for grinding wheel can be carried conveniently. In addition, measurements can be performed by users on the site where the grinding wheel is located for real-timely understanding the real size and wear condition of grinding wheel.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 1, 2022
    Assignee: Metal Industries Research & Development Centre
    Inventors: Chin-Kang Chen, Ching-An Lin, Chia-Ho Cheng, Sung-Liang Hsieh, Chih-Hsin Chang
  • Publication number: 20220285295
    Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Wei-Han CHIANG, Ming-Da CHENG, Ching-Ho CHENG, Wei Sen CHANG, Hong-Seng SHUE, Ching-Wen HSIAO, Chun-Hung CHEN
  • Publication number: 20220068868
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Application
    Filed: November 8, 2021
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Nong WEN, Ching-Han HUANG, Ching-Ho CHANG
  • Patent number: 11171108
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 9, 2021
    Inventors: An-Nong Wen, Ching-Han Huang, Ching-Ho Chang
  • Publication number: 20200111761
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 9, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Nong WEN, Ching-Han HUANG, Ching-Ho CHANG
  • Patent number: 10469816
    Abstract: A projection system, a display system and monitoring methods thereof are provided. The projection system includes at least one projection device, at least one sensing device and a remote device. The at least one projection device is coupled to the at least one sensing device. The at least one sensing device senses a plurality of environmental parameters and a plurality of device output values on the at least one projection device. The remote device receives the environmental parameters and the device output values to execute state analysis for the at least one projection device, so as to generate at least one analysis result. The remote device further generates a command signal according to the at least one analysis result, and transmits the command signal to the at least one projection device. The at least one projection device executes a self-protection procedure according to the command signal.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 5, 2019
    Assignee: Coretronic Corporation
    Inventors: Hsin-Ya Lai, Jui-Chi Chen, Fu-Shan Wang, Heng-CHeng Chen, Chueh-Ching Chen, Ching-Ho Chang
  • Publication number: 20190124310
    Abstract: A projection system, a display system and monitoring methods thereof are provided. The projection system includes at least one projection device, at least one sensing device and a remote device. The at least one projection device is coupled to the at least one sensing device. The at least one sensing device senses a plurality of environmental parameters and a plurality of device output values on the at least one projection device. The remote device receives the environmental parameters and the device output values to execute state analysis for the at least one projection device, so as to generate at least one analysis result. The remote device further generates a command signal according to the at least one analysis result, and transmits the command signal to the at least one projection device. The at least one projection device executes a self-protection procedure according to the command signal.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 25, 2019
    Applicant: Coretronic Corporation
    Inventors: Hsin-Ya Lai, Jui-Chi Chen, Fu-Shan Wang, Heng-Cheng Chen, Chueh-Ching Chen, Ching-Ho Chang
  • Publication number: 20190102134
    Abstract: Disclosed are a display system, a display device and a display method of a display system. A main display device corrects display properties of a displayed image of a secondary display device according to display properties of a displayed image of the main display device, so as to adjust the displayed image of the secondary display device to have the same display properties as the displayed image of the main display device, thereby effectively improving the convenience of use of the display system and the display device.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 4, 2019
    Applicant: Coretronic Corporation
    Inventors: Chueh-Ching Chen, Jui-Chi Chen, Fu-Shan Wang, Hsin-Ya Lai, Ching-Ho Chang, Heng-Cheng Chen
  • Patent number: 9964987
    Abstract: A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N. The first transistors have the same channel length, and the second transistors have the same channel length.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
  • Publication number: 20160266597
    Abstract: A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N. The first transistors have the same channel length, and the second transistors have the same channel length.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventors: Ching-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
  • Patent number: 9383264
    Abstract: A thermal sensing system includes a circuit having a layout including standard cells arranged in rows and columns. First and second current sources provide first and second currents, respectively. The thermal sensing system includes thermal sensing units, first and second switching modules, and an analog to digital converter (ADC). Each thermal sensing unit is configured to provide a voltage drop dependent on a temperature at that thermal sensing unit. The first switching module is configured to select one of the thermal sensing units. The second switching module includes at least one switch controllable by a control signal. The at least one switch is configured to selectively couple the thermal sensing units, based on the control signal, to one of the first and second current sources, via the first switching module. The ADC is configured to convert an analog voltage, provided by the selected thermal sensing unit, to a digital value.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Ching-Ho Chang, Jui-Cheng Huang
  • Patent number: 9379112
    Abstract: An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
  • Patent number: 9350372
    Abstract: Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Ho Chang, Yung-Chow Peng, Jui-Cheng Huang, Wen-Shen Chou
  • Publication number: 20150241902
    Abstract: An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 27, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Ching-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
  • Patent number: 9016939
    Abstract: Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: April 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Ho Chang, Jui-Cheng Huang, Yung-Chow Peng
  • Patent number: 8884797
    Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chow Peng, Jui-Cheng Huang, Ching-Ho Chang, Nang Ping Tu
  • Publication number: 20140159932
    Abstract: Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Ho Chang, Yung-Chow Peng, Jui-Cheng Huang, Wen-Shen Chou
  • Publication number: 20140092939
    Abstract: Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Inventors: Ching-Ho Chang, Jui-Cheng Huang, Yung-Chow Peng
  • Publication number: 20130195142
    Abstract: A thermal sensing system includes a circuit having a layout including standard cells arranged in rows and columns. First and second current sources provide first and second currents, respectively. The thermal sensing system includes thermal sensing units, first and second switching modules, and an analog to digital converter (ADC). Each thermal sensing unit is configured to provide a voltage drop dependent on a temperature at that thermal sensing unit. The first switching module is configured to select one of the thermal sensing units. The second switching module includes at least one switch controllable by a control signal. The at least one switch is configured to selectively couple the thermal sensing units, based on the control signal, to one of the first and second current sources, via the first switching module. The ADC is configured to convert an analog voltage, provided by the selected thermal sensing unit, to a digital value.
    Type: Application
    Filed: March 23, 2012
    Publication date: August 1, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow PENG, Ching-Ho CHANG, Jui-Cheng HUANG
  • Patent number: 8476971
    Abstract: A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: July 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Wen-Shen Chou, Ching-Ho Chang, Wan-Te Chen