Abstract: Systems and methods that provide reconfigurable shifter configurations supporting multiple instruction, multiple data (MIMD) are described. Shifters implemented according to embodiments support multiple data shifts with respect to an instance of data shifting, wherein multiple individual different data shifts are implemented at a time in parallel. Reconfigurable segmented scalable shifters of embodiments, in addition being reconfigurable for scalability in supporting data shifting with respect to various bit lengths of data, are configured to support data shifting of differing bit lengths in parallel. The data shifters of embodiments implement segmentation for facilitating data shifting with respect to differing bit lengths. Different data shift commands may be provided with respect to each such segment, thereby facilitating multiple data shifts in parallel with respect to various bit lengths of data.

Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation.

Abstract: Systems and methods that provide reconfigurable shifter configurations supporting multiple instruction, multiple data (MIMD) are described. Shifters implemented according to embodiments support multiple data shifts with respect to an instance of data shifting, wherein multiple individual different data shifts are implemented at a time in parallel. Reconfigurable segmented scalable shifters of embodiments, in addition being reconfigurable for scalability in supporting data shifting with respect to various bit lengths of data, are configured to support data shifting of differing bit lengths in parallel. The data shifters of embodiments implement segmentation for facilitating data shifting with respect to differing bit lengths. Different data shift commands may be provided with respect to each such segment, thereby facilitating multiple data shifts in parallel with respect to various bit lengths of data.

Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation.

Abstract: Methods and systems which provide for synchronization target selection by configuring a network device to reselect a synchronization signal transmission timeslot for synchronization target searching by the network device are described. Synchronization signal timeslot reselection may provide for downgrading a current stratum index to an artificial stratum index that does not accurately indicate a number of hops between the network device and a global synchronization source to allow for selection of available synchronization targets with stratum indices that are higher than or equal to the network device's stratum index without causing a synchronization loop. A synchronization signal pattern cycle structure having synchronization signal timeslots organized into multiple subcycles for accommodating synchronization signal timeslot reselection is utilized according to embodiments.

Abstract: Methods and systems which provide for synchronization target selection by configuring a network device to reselect a synchronization signal transmission timeslot for synchronization target searching by the network device are described. Synchronization signal timeslot reselection may provide for downgrading a current stratum index to an artificial stratum index that does not accurately indicate a number of hops between the network device and a global synchronization source to allow for selection of available synchronization targets with stratum indices that are higher than or equal to the network device's stratum index without causing a synchronization loop. A synchronization signal pattern cycle structure having synchronization signal timeslots organized into multiple subcycles for accommodating synchronization signal timeslot reselection is utilized according to embodiments.