Abstract: An erasable programmable read only memory includestwo serially connected P-type metal-oxide semiconductor (MOS) transistors,wherein a first P-type MOS transistor acts as selecttransistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the firstP-type MOS transistor connected to source linevoltage, a second node of the first P-type MOS transistor connected to a first node of a second P-type MOS transistor, wherein a second node of the second P-type MOS transistor is connected to bit line voltage, wherein a gate of the secondP-type MOS transistor serves as a floating gate, wherein the erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto the floating gate, and wherein the erasable programmable read only memory is capped by dielectric materials which are transparent to ultraviolet (UV) light.

Abstract: A novel structure of nonvolatile memory is disclosed. The nonvolatile memory includes two serially connected PMOS transistors. The characteristic of the devices is that bias is not necessary to apply to the floating gate during the programming mode. Thus, the control gate is omitted for the structure or layout, thereby saving the space for making the control gate. The carrier may be “automatically injected” into floating gate for programming the status of the devices.

Abstract: A flash memory array and related method for programming, erasing, and reading. The memory includes: a plurality of memory cells, each memory cell having a gate, a drain, a source, and a body; a plurality of word lines and body lines. The bodies of the memory cells whose gates are connected to a same word line are connected to a same body line, and the body lines are isolated from each other such that different body lines can be driven to have different voltages. When the memory programs, erases, and reads data, the different body lines are driven to different voltage.

Abstract: A low-voltage nonvolatile memory array includes an N type semiconductor substrate having a memory region. A deep P well is formed in the semiconductor substrate. A cell N well is located within the memory region in the semiconductor substrate. The cell N well is situated above the deep ion well. A shallow P well serving as a buried bit line is doped within the cell ion well. The shallow P well is isolated by an STI layer, wherein the STI layer has a thickness greater than a well depth of the shallow ion well. At least one memory transistor with a stacked gate, a source, and a drain is formed on the shallow ion well. The source of the memory transistor is electrically coupled to the cell N well to induce a capacitor between the cell N well and the deep P well during a read operation, thereby avoiding read current bounce or potential power crash.

Abstract: A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p+ doped region, a second p+ doped region, and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, and forming a p+ floating gate between the second p+ doped region and the third p+ doped region.

Abstract: A hinge for a notebook computer is composed of a first seat, a second seat and an axle. The first seat is mounted on a monitor, and the second seat is mounted on a body. The axle is securely mounted on the first seat and pivotally mounted on the second seat. Two sleeves are provided outside the axle and engaged with each other in a closed status. The first sleeve has two lugs received in a channel defined in the second sleeve. The second sleeve has two protrusive portions respectively formed at two sides of the channel, and two cambered surfaces formed between the channel and the protrusive portion. When a user lowers the monitor to a position that the lugs enter into the cambered surfaces, the monitor can automatically descend under the effect of gravity and the force of a resilient member.

Abstract: A non-volatile semiconductor memory device having divided bit lines. A main bit line is controlled by at least one bit line selection device to transfer its potential to a selected sub bit line, such that memory cells in a selected sector work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device are arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.

Abstract: The invention advantageously provides an alert system and method for geographic or natural disasters that utilize a telecommunications network for monitoring geographic data in disaster-prone areas and accordingly issuing warnings against potential disasters to people inside the monitored area. An alert system according to a preferred embodiment of the invention comprises a telecommunications service network, one or more wireless sensor modules and a control center. The telecommunications network according to this particular embodiment includes service coverage over the monitored areas. The wireless sensor modules are installed to selected locations inside monitored areas. Each of the sensor modules further comprises at least one sensor for collecting geographic or geodetic data and a wireless communications unit for sending collected geographic data to the control center via the telecommunications network.

Abstract: The invention provides an authentication, authorization and accounting (AAA) a system and method for a plurality of wireless local area networks (WLANs) operated by a plurality of WLAN operators comprising a mobile communications device connecting to a terminal comprising an Internet access application program for accessing the Internet, a personal identification number (PIN) application program, and a unique identifier application program. An Internet access session is requested from the mobile device by activating the Internet access application program in the terminal. Entry of a PIN is requested by activating the PIN application program in the terminal, wherein the PIN is authenticated.

Abstract: The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, wherein flash memory cell structures and CMOS devices are simultaneously fabricated on a substrate to reduce the cost and to simplify the process flow. Moreover, CMOS devices capable of performing high-voltage and low-voltage operations are reserved. Therefore, the present invention can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.

Abstract: A flash memory structure and method of fabrication is introduced. The flash memory structure includes a plurality of parallel word lines positioned on a semiconductor substrate, a plurality of parallel source lines with first conductivity type positioned perpendicularly to the word lines and within the semiconductor substrate, two bit lines with first conductivity type positioned on two sides of each source line and within the semiconductor substrate, a doped region with second conductivity type positioned beneath and surrounding each bit line, a contact plug positioned in each bit line for electrically connecting to the bit line and a corresponding doped region beneath and surrounding the bit line, and a gate positioned on an overlapped region of the semiconductor substrate and each word line.

Abstract: A single-poly EEPROM is disxlosed. The single-poly EEPROM includes a first PMOS transistor that is serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region, and a first P+ doped source region. The second PMOS transistor includes a gate and second P+ doped source region. The first P+ doped source region of the first PMOS trasistor serves as a drain of the second PMOS transistor. An erase gate extending to the floating gate for erasing the single-poly EEPROM is provided in the P-type substrate.

Abstract: A non-volatile semiconuctor memory device having divided bit lines. A main bit line controlled by at least one bit line selection device to transfer its potential selected sub bit line, such that memory cells in a selected work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.

Abstract: The present invention provides a method for treating allergy in a subject comprising administrating said subject with a medicament comprising a lactic acid bacterial strain stimulating INF-&ggr; secretion, which is selected from the group consisting of Lactobacillus plantarum CCRC 12944, Lactobacillus acidophilus CCRC 14079, Lactobacillus rhamnosus CCRC 10940, Lactobacillus paracasei subsp. paracasei CCRC 14023, Lactobacillus delbrueckii subsp. bulgaricus CCRC 12297, Lactobacillus delbrueckii subsp. bulgaricus CCRC 14007, and Lactobacillus delbrueckii subsp. bulgaricus CCRC 14069. A composition for treating allergy comprising the above-mentioned lactic acid bacterial strain is also provided.

Abstract: The present invention mainly relates to a process of creating an index for diagnosis and/or prognosis of a complex disease trait by using a correlation formula obtained by the statistic analysis and regression process for condition scores and the expression values of the gene selected to be related to the complex disease trait. A process of creating an asthma index for diagnosis and/or prognosis of asthma is also provided in the invention.

Abstract: An erasable programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode.

Abstract: The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well. A deep p-type region and a shallow p-type region are ion-implanted in the N-well. The deep p-type region is connected to the shallow p-type region. An n-type region is ion-implanted in the deep p-type region to be electrically shorted with the deep p-type region and be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source.

Abstract: The present invention provides a method of facilitating the diagnosis, monitoring and treatment of a human patient by measuring the ECP level in the patient's blood, and determining whether the patient is within the heat pattern group or the non-heat pattern group based on the measure ECP level.

Abstract: A single-poly EEPROM is disclosed. The single-poly EEPROM includes a first PMOS transistor that is serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region, and a first P+ doped source region. The second PMOS transistor includes a gate and second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. An erase gate extending to the floating gate for erasing the single-poly EEPROM is provided in the P-type substrate.

Abstract: A hinge bracket has a positioning disk adapted to be abutted to one side of the leg of the frame and having a first cutout and a second cutout peripherally defined around the positioning disk and a pad sandwiched between the positioning disk and one of the second leaf springs. The pad has a finger alternately corresponding to the first cutout and the second cutout so that the frame is able to be supported at a first position or the frame is able to be extended at a second position to be in parallel with the base to minimize space taken when stored or transported.