Abstract: A one-time programmable memory structure comprises: A transistor includes a gate. A capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is disposed on the first electrode. A top surface of the first electrode and a top surface of the gate are located on a same plane perpendicular to a direction of the first electrode toward the second electrode. An interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode. A resistor comprises a conductive layer. Top and bottom surfaces of the conductive layer are respectively located on a same plane, perpendicular to the direction of the first electrode toward the second electrode, with the top and bottom surfaces of the gate.

Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

Abstract: An LED lamp includes a mounting seat, a circuit board mounted in the mounting seat, a plurality of primary LED lights mounted on the circuit board, a light permeable frame mounted on the mounting seat, and a shade mounted on the light permeable frame. The mounting seat is provided with a light guide face corresponding to an inner peripheral face of the light permeable frame. The light rays of the primary LED lights permeate through the shade and irradiate downward in a perpendicular manner, and are guided by the light guide face of the mounting seat, pass through the light permeable frame and are diffused and emitted sideward from the shade in an angle of one hundred and eighty degrees (180°) to expand the illuminating angle and range of the primary LED lights.

Abstract: An LED bulb contains: a first shell, a second shell, a heat dissipating element fixed between the first shell and the second shell. The dissipating element includes a first substrate and a second substrate which correspond to the first shell and the second shell, wherein the first substrate includes at least one first LED lighting element, and the second substrate includes at least one second LED lighting element, such that lights illuminate out of the second shell and the first shell via a plurality of heat dissipation fins, thus having omnidirectional illumination. The at least one first LED lighting element of the first substrate illuminates the lights at 180 degrees. Preferably, the second shell is a sphere-shaped shell, a semi-arcuate shell or a flat shell to satisfy different using requirements.

Abstract: An electrical fuse structure includes a top conductive pattern having a top fuse and a top fuse extension portion, a bottom conductive pattern having a bottom fuse and a bottom fuse extension portion corresponding to the top fuse extension portion, and a via conductive layer positioned between the top fuse extension portion and the bottom fuse extension portion for electrically connecting the top fuse extension portion and the bottom fuse extension portion.

Abstract: An electrical fuse structure includes a top conductive pattern having a top fuse and a top fuse extension portion, a bottom conductive pattern having a bottom fuse and a bottom fuse extension portion corresponding to the top fuse extension portion, and a via conductive layer positioned between the top fuse extension portion and the bottom fuse extension portion for electrically connecting the top fuse extension portion and the bottom fuse extension portion.

Abstract: An electrical fuse structure includes a top fuse, a bottom fuse and a via conductive layer positioned between the top fuse and the bottom fuse for providing electric connection. The top fuse includes a top fuse length and the top fuse length is equal to or larger than a predetermined value. The bottom fuse includes a bottom fuse length larger than the top fuse length.

Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.

Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.

Abstract: A fluorescent lamp including a tube, a fluorescent layer, a discharging gas and two electrodes is provided. The fluorescent layer is disposed on an inner wall of the tube. The fluorescent layer has a plurality of patterned grooves to form a serial number. The discharging gas is distributed in the tube. In addition, the electrodes are disposed at two ends of the tube.

Abstract: In an embodiment, a phosphor material composition comprises a phosphor powder and an additive, wherein the additive has an amount in a range of about 0.1%˜20% of the phosphor powder in weight. The material of the additive is selected from the group consisting of an energy absorption material and a conductive material and a combination thereof. In another embodiment, a phosphor material composition including a phosphor powder and an additive is provided, wherein the additive has an amount of 2.8 ppm˜32000 ppm. The material of the additive is also selected from the group consisting of an energy absorption material, a conductive material and a combination thereof.

Abstract: In a shadow mask employed as a color selection electrode in a multi-electron beam color cathode ray tube (CRT), the surface area of the mask is reduced by increasing the length of the individual elongated beam passing apertures, or slots, while reducing the ratio of the width of the bridge portion of the mask between adjacent apertures to the length of the aperture. Increasing the length of the apertures while reducing the ratio of bridge width to aperture length reduces the surface area of the mask upon which energetic electrons are incident resulting in a corresponding reduction in thermal deformation, or doming, of the shadow mask. Reduction in shadow mask doming results in reduced landing shift of the electron beams incident on phosphor elements disposed on the inner surface of the CRT's display screen for improved video image brightness and color purity. More specifically, in a shadow mask having a thickness in the range of 0.12-0.

Abstract: A shadow mask, or color selection electrode, in a color cathode ray tube (CRT) is in the form of a thin metal foil and includes a large number of apertures through which electron beams are directed onto the phosphorescent coating on the CRT's display screen for forming a video image. The apertured shadow mask is also used with a light source during CRT manufacture to form a large number of spaced phosphor elements in the phosphorescent coating. Ideally, all of the beam passing apertures and phosphor elements are circular in cross-section, but the shadow mask is stretched and maintained under high tension when mounted in the CRT causing some of the apertures, particularly those adjacent its four corners, to also become stretched and assume an oval shape.