Abstract: A frequency jittering control circuit wherein by means of the characteristics of a PLL whose input switches between different frequencies, the output frequency of the PLL swings between the different frequencies to achieve the desired frequency jittering.

Abstract: A linear voltage regulator comprises a transistor for converting a supply voltage to an output voltage. By directly monitoring the supply voltage and thereby rapidly responding when the supply voltage suffers a ripple, the linear voltage regulator enhances the stability of the output voltage.

Abstract: Time-sharing technique is used for power conversion to improve the thermal dissipation thereof. In a power supply arrangement to provide a supply voltage to a load, a plurality of linear regulators are so switched that each time only one of them is enabled to convert an input voltage to the supply voltage, thereby each of them suffering less thermal dissipation.

Abstract: A device for automatic error detection on booting a motherboard includes a storage device, and an automatic error detection speech unit. The storage device stores BIOS program code and a system status table for the motherboard, the BIOS program code being executed by a processor when the motherboard is booting, the system status table of the motherboard storing at least one motherboard element status, the motherboard status being updated by the processor when the motherboard is turned on in accordance with current conditions of the booting. The automatic error detection speech unit couples to the storage device for reading the system status table of the motherboard after a predetermined time period of the motherboard being turned on, and playing corresponding speech data in accordance with the motherboard status of the system status table for the motherboard.

Abstract: For protecting a power system, two or three of over current, thermal and under voltage protection circuits are integrated as one protection circuit but operate independently, and one or more protection points thereof are adjusted dynamically in response to detected condition of the power system. Specifically, using voltage and current conditions in the power system to modify the over current protection and the thermal protection maximizes the performance of the power system and covers the process bias in the circuits.

Abstract: A device for automatic error detection on booting a motherboard includes a storage device, and an automatic error detection speech unit. The storage device stores BIOS program code and a system status table for the motherboard, the BIOS program code being executed by a processor when the motherboard is booting, the system status table of the motherboard storing at least one motherboard element status, the motherboard status being updated by the processor when the motherboard is turned on in accordance with current conditions of the booting. The automatic error detection speech unit couples to the storage device for reading the system status table of the motherboard after a predetermined time period of the motherboard being turned on, and playing corresponding speech data in accordance with the motherboard status of the system status table for the motherboard.

Abstract: A constant current source with threshold voltage and channel length modulation includes first, second, third, fourth and fifth MOS transistors. Each of the MOS transistors has gate, first and second terminals. The first terminal of the second MOS transistor is coupled to loading impedance, and its second terminal is coupled with the first terminal of the first MOS transistor. The gate terminal and first terminal of the third MOS transistor are together coupled to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage.

Abstract: A constant current source with threshold voltage and channel length modulation includes first, second, third, fourth and fifth MOS transistors. Each of the MOS transistors has gate, first and second terminals. The first terminal of the second MOS transistor is coupled to loading impedance, and its second terminal is coupled with the first terminal of the first MOS transistor. The gate terminal and first terminal of the third MOS transistor are together coupled to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage.

Abstract: A multiple-delay variable delay circuit uses a random access memory (RAM) array to provide adjustable delay of a block of input data, such as previously necessitated use of an extensive shift register configuration. A single RAM array, having a given capacity, is used to economically provide individual delays to a plurality of blocks of input data, with the aggregate of the individual delays not exceeding the capacity of the single RAM array. Time-shared use of a high speed RAM enables simultaneous single-port processing of data blocks, with delay control circuits providing utilization of separate portions of the RAM capacity, to provide individual delays resulting from successive read/write cycles utilizing a desired total of incremental delays. Simplified delay control circuits provide manufacturing and operating economies with single-port or multi-port RAM arrays.

Abstract: A pipeline multiplier is used for multiplying a multiplicand to a multiplier. The pipeline multiplier includes a plurality of adder stages each adder stage includes a partial product processor for processing a partial product of the multiplicand and one of the multiplier. Each of the adder stages further includes a plurality of ripple carry adder (RCA) bands each band includes a plurality of full adders wherein the carry of the full adders ripple sequentially to the most significant full adder in the RCA band. Furthermore, each of the RCA bands in each adder stage includes approximately same number of full adders. The adder stages are further arranged in sequential order such that each of the RCA bands in each stage are pipelined to a corresponding RCA band, which is a RCA band being more-significantly-shifted by one bit, in next adder stage according to the sequential order whereby an accumulative partial product is propagated from one of the adder stages to a next stage.

Abstract: The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus includes an input port for receiving the ordered sequence of input data and the variable-length delay-time. The apparatus further includes an integrated data storage, a random access memory (RAM) for storing the ordered sequence of input data according to a storage-order corresponding to the ordered sequence of the input data. The apparatus further includes a delay output port for accessing and outputting the delay output item in the storage means according to the variable-length delay-time and the storage-order such that the delay output item is delayed by the variable-length delay-time.