Patents by Inventor Ching-Hsu Chang
Ching-Hsu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136227Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
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Patent number: 11901286Abstract: A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.Type: GrantFiled: May 28, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wei Peng, Chih-Min Hsiao, Ching-Hsu Chang, Jiann-Tyng Tzeng
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Publication number: 20230387002Abstract: An integrated circuit (IC) structure includes a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks, a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks, and a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Shih-Wei PENG, Chih-Min HSIAO, Ching-Hsu CHANG, Jiann-Tyng TZENG
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Publication number: 20220237357Abstract: A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.Type: ApplicationFiled: May 28, 2021Publication date: July 28, 2022Inventors: Shih-Wei PENG, Chih-Min HSIAO, Ching-Hsu CHANG, Jiann-Tyng TZENG
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Patent number: 11048161Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.Type: GrantFiled: December 27, 2019Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chun Wang, Chi-Ping Liu, Feng-Ju Chang, Ching-Hsu Chang, Wen Hao Liu, Chia-Feng Yeh, Ming-Hui Chih, Cheng Kun Tsai, Wei-Chen Chien, Wen-Chun Huang, Yu-Po Tang
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Patent number: 10747938Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.Type: GrantFiled: July 19, 2019Date of Patent: August 18, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan Wu, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
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Publication number: 20200142294Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.Type: ApplicationFiled: December 27, 2019Publication date: May 7, 2020Inventors: Hung-Chun Wang, Chi-Ping Liu, Feng-Ju Chang, Ching-Hsu Chang, Wen Hao Liu, Chia-Feng Yeh, Ming-Hui Chih, Cheng Kun Tsai, Wei-Chen Chien, Wen-Chun Huang, Yu-Po Tang
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Patent number: 10527928Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.Type: GrantFiled: July 19, 2017Date of Patent: January 7, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chun Wang, Chi-Ping Liu, Feng-Ju Chang, Ching-Hsu Chang, Wen Hao Liu, Chia-Feng Yeh, Ming-Hui Chih, Cheng Kun Tsai, Wei-Chen Chien, Wen-Chun Huang, Yu-Po Tang
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Publication number: 20190340330Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan WU, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
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Patent number: 10360339Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.Type: GrantFiled: February 15, 2016Date of Patent: July 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan Wu, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
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Publication number: 20180173090Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.Type: ApplicationFiled: July 19, 2017Publication date: June 21, 2018Inventors: Hung-Chun Wang, Chi-Ping Liu, Feng-Ju Chang, Ching-Hsu Chang, Wen Hao Liu, Chia-Feng Yeh, Ming-Hui Chih, Cheng Kun Tsai, Wei-Chen Chien, Wen-Chun Huang, Yu-Po Tang
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Patent number: 9880460Abstract: The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.Type: GrantFiled: July 15, 2016Date of Patent: January 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Ching-Hsu Chang, Nian-Fuh Cheng, Chih-Shiang Chou, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20160327854Abstract: The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.Type: ApplicationFiled: July 15, 2016Publication date: November 10, 2016Inventors: Ching-Hsu Chang, Nian-Fuh Cheng, Chih-Shiang Chou, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20160221837Abstract: An indoor/outdoor water filtering apparatus having a pump electrically connected to a power device supplied by an external power source or a rechargeable battery with a switch for user selection of a plurality of operating modes for filtering water in different environments, wherein a first mode electrically connects a first loop with a first pressure sensor cutting off power when water pressure exceeds an upper limit, a second mode cuts off power, and a third mode electrically connects a second loop with a second pressure sensor cutting off power when water pressure is lower than a lower limit.Type: ApplicationFiled: February 2, 2015Publication date: August 4, 2016Applicants: JAM HOM CO.,LTD., National Yunlin University of Science & TechnologyInventor: CHING-HSU CHANG
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Patent number: 9395618Abstract: The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.Type: GrantFiled: July 24, 2015Date of Patent: July 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hsu Chang, Nian-Fuh Cheng, Chih-Shiang Chou, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20160162627Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.Type: ApplicationFiled: February 15, 2016Publication date: June 9, 2016Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan WU, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
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Patent number: 9357453Abstract: A home base station and method for supporting a plurality of cells under carrier aggregation. The home base station includes a preamble generator and a preamble monitor. The preamble generator allocates respective random access resources in the cells for handover to be carried out by a user equipment (UE), and upon receiving a handover request signal transmitted by a Mobility Management Entity (MME), generates a specific preamble and its transmission time, so that the UE performs random access on the cells based on the preamble and the transmission time to obtain the random access resources and sends out a Random Access Preamble (RAP). The preamble monitor enables the cells to simultaneously monitor the RAP sent by the UE, and when one of the cells receiving the RAP, identifies the cell on which the UE camps based on which one of the cells that has the RAP.Type: GrantFiled: May 27, 2014Date of Patent: May 31, 2016Assignee: Industrial Technology Research InstituteInventors: Chia-Lung Liu, Kuei-Li Huang, Ching-Hsu Chang
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Patent number: 9298083Abstract: An extreme ultraviolet photomask comprises a reflective layer over a substrate, a capping layer over the reflective layer, a hard mask layer over the capping layer, and an absorber. The absorber is in the hard mask layer, the capping layer and the reflective layer.Type: GrantFiled: May 16, 2014Date of Patent: March 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Hsu Chang, Hung-Chun Wang, Boren Luo, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 9262578Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.Type: GrantFiled: June 2, 2014Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Feng-Ju Chang, Chun-Hung Wu, Ping-Chieh Wu, Wen-Hao Liu, Ming-Hsuan Wu, Feng-Lung Lin, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20150331333Abstract: The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: Ching-Hsu Chang, Nian-Fuh Cheng, Chih-Shiang Chou, Wen-Chun Huang, Ru-Gun Liu