Abstract: The present disclosure provides a bias clamp circuit, which includes a plurality of switchable clamp voltage paths, configured to selectively clamp a gate bias voltage of a vulnerable circuit to a first voltage or a second voltage based on whether a reliability acceleration test is performed on the vulnerable circuit or not. The second voltage is higher than the first voltage.

Abstract: A noise suppression circuit is provided. The noise suppression circuit is provided between a transmission interface and a receiving interface. In particular, the transmission interface includes a digital interface, a power transmission interface, or a combination thereof. The noise suppression circuit includes a first noise suppression component and a second noise suppression component. The second noise suppression component is connected to the first noise suppression component through a phase adjusting component. Some signals on the transmission interface are transmitted to the receiving interface through the first noise suppression component, the phase adjusting component and the second noise suppression component. As a result, interference from the transmission interface to the receiving interface is suppressed.

Abstract: A composite material structure, including an outer layer, an inner layer, a middle layer, a protective layer, and an anodized layer, is provided. The outer layer includes a first metallic material and has an outer surface and an inner surface opposite to each other. The inner layer includes a fiber composite material composed of a fiber material and a resin material, a second metallic material, or a metal fiber composite material composed of the fiber composite material and the second metallic material. The middle layer includes an adhesive material and is disposed between the outer layer and the inner layer. The protective layer includes an anodization-resistant material and is disposed on the inner layer. The anodized layer is located on the outer surface and is an oxide film composed of the first metallic material. A manufacturing method thereof is also provided.

Abstract: A one-time programmable (OTP) memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell of the plurality of memory cells including a first terminal coupled to a bit line of the plurality of bit lines, a second terminal coupled to a word line of the plurality of word lines, and a selector coupled between the first terminal and the second terminal and having a threshold voltage that is alterable by an electric current.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a channel structure and a gate stack wrapped around the channel structure. The semiconductor device structure also includes an epitaxial structure adjacent to the channel structure. The epitaxial structure includes a main portion and a lower portion below the main portion. A top of the channel structure is vertically between a top of the main portion and a bottom of the main portion, and the main portion and the lower portion are oppositely doped.

Abstract: A fog discrimination method is disclosed, including a capturing step, a calculation step, and a determining step. The capturing step includes capturing a sub-image of an image. The sub-image includes a light shield body image and a light shield stripe image. The calculation step includes calculating a maximum average grayscale value and a minimum average grayscale value of the sub-image; and calculating a fog function. The fog function is a function of the maximum average grayscale value and the minimum average grayscale value. The determining step includes determining whether the fog function is greater than or less than a threshold; and determining as being fogged when the fog function is less than the threshold.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first gate structure over a substrate, and the first gate structure includes a first metal electrode. The method includes forming a second gate structure adjacent to the first gate structure, and the second gate structure includes a second metal electrode. The method also includes forming a mask structure covering the first gate structure and exposing the second gate structure, and etching a portion of the second metal electrode of the second gate structure to form an extending conductive portion. The method includes forming a metal layer over the first gate structure and the extending conductive portion, and etching the metal layer, such that no metal layer is remaining over the first gate structure, and a remaining portion of the metal layer is over the extending conductive portion.

Abstract: Provided are identifies new methods for regulating (or reprogramming) glycolytic reaction by using alpha-enolase (ENO-1) antagonist or agonist. More specifically, provided are methods for glycolysis reprogramming by targeting extracellular ENO-1 or membrane-associated ENO-1.

Abstract: A load switch circuit is provided. The load switch circuit includes a control chip and a current limit protection circuit. The control chip is operated at a power supply voltage, configured to receive an input voltage, and controlled by an enable signal to provide an output voltage and an output current to a load. The current limit protection circuit is configured to provide a current limit control voltage to a current limit and low power pin of the control chip, so that the control chip may adjust a current limit of the output current.

Abstract: A cooling motor includes a motor device having a motor casing, a motor assembly arranged in the motor casing, and a centrifugal fan, and a cooling device having first and second cooling components. The first cooling component includes a first cold plate jacket and a first heat circulation pipeline. The first cold plate jacket is sleeved on the motor assembly and thermally connected to a stator, and the first cold plate jacket includes first cold plates. The first thermal circulation pipeline filled with a first working fluid passes through the first cold plate jacket. The second cooling component includes a second cold plate jacket and a second heat circulation pipeline. The second cold plate jacket, sleeving the first cold plate jacket in an insulation manner, includes second cold plates and cooling fins. The second thermal circulation pipeline filled with a second working fluid passes through the second cold plate jacket.

Abstract: In some implementations, a memory device may program host data to memory using a program scheme, including by permitting, during a first programming pulse, a memory cell to receive a first program voltage; and by inhibiting, during a second and third programming pulse, the memory cell from receiving a second and third program voltage, respectively. The memory device may verify the program scheme using a majority vote program verify scheme, including by performing a first, second, and third program verify procedure for the memory cell following the first, second, and third programming pulse, respectively; and by determining whether the memory cell passes a majority of the first, second, and third program verify procedures. The memory device may inhibit or permit the memory cell to receive a fourth program voltage based on whether the memory cell passes the majority of the first, second, and third program verify procedures.

Abstract: A semiconductor structure includes a first electrode, a second electrode and a dielectric layer. The second electrode is disposed over the first electrode. The dielectric layer is disposed between the first electrode and the second electrode, and is configured to store information, wherein a bandgap at a first surface of the dielectric layer facing the first electrode is greater than a bandgap at a second surface of the dielectric layer facing the second electrode. A method of manufacturing the semiconductor structure is also provided.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first semiconductor device and second semiconductor device disposed on a semiconductor substrate. The first semiconductor device comprises a first gate structure, a first source region, and a first drain region. The first source and drain regions and are disposed in a first well region. The second semiconductor device comprises a second gate structure, a second source region, and a second drain region. The second source and drain regions are disposed in a second well region. The first and second well regions comprise a first doping type. The first well region is laterally offset from the second well region by a first distance. A third well region is disposed in the semiconductor substrate and laterally between the first and second well regions. The third well region comprises a second doping type opposite the first doping type.

Abstract: A semiconductor device includes a radio frequency (RF) switch and a shielding layer between the RF switch and a semiconductor substrate of the semiconductor device. The shielding layer suppresses electric field emissions and/or magnetic field emissions generated by the RF switch, which prevents, minimizes, and/or otherwise reduces the likelihood of the electric field emissions and/or the magnetic field emissions causing a parasitic current to be induced in the semiconductor substrate. In this way, the shielding layer described herein reduces, minimizes, and/or prevents harmonic distortion in the operation of the RF switch. This enables the RF switch to maintain linear operation, which enables more accurate and faster switching for the RF circuit.

Abstract: An oral scanner system having an oral scanner, the oral scanner having a handle, a head, a camera, a spacer attachment being detachably attached to the head, and a processor being arranged to receive at least one signal from the camera to determine, based on an analysis of the at least one signal, an attachment state of the spacer attachment.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.

Abstract: Control logic in a memory device receives a request to perform a memory access operation on a memory array of the memory device and determines an operating temperature of the memory device. The control logic further modifies a default magnitude of a source voltage signal based on the operating temperature to a form a modified source voltage signal, causes the modified source voltage signal to be applied to the memory array, and performs the memory access operation on the memory array.