Abstract: A liquid crystal on silicon display panel and a method for manufacturing the same are disclosed. The method includes the following steps. First, a semiconductor substrate having a pixel region with at least one first top metal pattern and a first anti-reflection coating structure substantially disposed thereon and a circuit region with is at least one second top metal pattern and a second anti-reflection coating structure substantially disposed thereon is provided. Moreover, the circuit region surrounds the pixel region. Next, the first anti-reflection coating structure is removed. Afterward, a dielectric layer is formed on the semiconductor substrate and covering the first top metal pattern. Then, a passivation layer is formed on the dielectric layer. After that, a portion of the passivation layer and a portion of the second anti-reflection coating structure thereunder are removed to form an opening exposing a portion of the second top metal pattern.

Abstract: A liquid crystal on silicon display panel and a method for manufacturing the same are disclosed. The method includes the following steps. First, a semiconductor substrate having a pixel region with at least one first top metal pattern and a first anti-reflection coating structure substantially disposed thereon and a circuit region with is at least one second top metal pattern and a second anti-reflection coating structure substantially disposed thereon is provided. Moreover, the circuit region surrounds the pixel region. Next, the first anti-reflection coating structure is removed. Afterward, a dielectric layer is formed on the semiconductor substrate and covering the first top metal pattern. Then, a passivation layer is formed on the dielectric layer. After that, a portion of the passivation layer and a portion of the second anti-reflection coating structure thereunder are removed to form an opening exposing a portion of the second top metal pattern.

Abstract: A capacitor disposed on a silicon substrate is disclosed. The silicon substrate has a first region, a second region, and a third region, which is adjacent to the first region and the second region, defined on its surface. The capacitor has a bottom electrode disposed in the first region and the third region on the surface of the silicon substrate, a dielectric layer disposed on the bottom electrode and the substrate, and a top electrode disposed in the second region and the third region on the surface of the dielectric layer.

Abstract: A mixed-mode process comprises to provide a substrate first. A surface of the substrate comprises at least a first conductor in a first conductive region, at least a second conductor in a second conductive region, at least a metal-oxide-semiconductor (MOS) transistor in a MOS transistor region, and at least a capacitor in a capacitor region. A mask is then formed on the substrate to expose the second conductor. A first etching process is thereafter performed to remove a specific thickness of the second conductor followed by a first ion implantation process to dope the second conductor with the first type dopants.

Abstract: A gate oxide layer, a first polysilicon layer, a polycide layer and a first interpolysilicon oxide (IPO) layer are sequentially formed on a semiconductor substrate. The first IPO layer, the polycide layer and the first polysilicon layer are then etched to form a gate and a bottom electrode plate. A second IPO layer and a polysilicon layer are then formed on the substrate and are etched to form a conductive wire and a top electrode plate thereafter. Finally, a spacer is formed, and an ion implantation process and a self-aligned suicide (salicide) process are performed to complete a mixed mode process for the formation of the conductive wire, a metal-oxide-semiconductor (MOS) transistor and a capacitor structure.

Abstract: A method of fabricating of a capacitor with low voltage coefficient of capacitance is described. A silicon substrate with field oxide isolations is provided. A buried layer is formed by doping N-type impurities into the substrate as the bottom plate of the capacitor. A dielectric layer is formed by thermal oxidation for the capacitor, and then a polysilicon layer is formed by the low pressure chemical vapor deposition method. A thermal diffusion step is performed to dope phosphorus into the polysilicon layer. After formation of a polysilicide layer by the low pressure chemical vapor deposition method, arsenic ions are implanted into the polysilicon layer and the polysilicide layer. Finally the polysilicide layer and the polysilicon layer are partially etched in consequence, and the top plate of the capacitor is formed.