Patents by Inventor Ching-Hung Chang
Ching-Hung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11948798Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.Type: GrantFiled: July 16, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang, Tze-Liang Lee
-
Publication number: 20240055390Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.Type: ApplicationFiled: October 23, 2023Publication date: February 15, 2024Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
-
Patent number: 11876077Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.Type: GrantFiled: March 12, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
-
Patent number: 11842979Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.Type: GrantFiled: March 11, 2021Date of Patent: December 12, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
-
Patent number: 11776924Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.Type: GrantFiled: December 9, 2021Date of Patent: October 3, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chiang-Lin Shih, Pei-Jhen Wu, Ching-Hung Chang, Hsih-Yang Chiu
-
Publication number: 20220293552Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
-
Publication number: 20220288231Abstract: This disclosure provides methods and pharmaceutical compositions for attenuating immune response in a subject suffering from a genetic disorder and receiving gene or nucleic acid therapy. The pharmaceutical compositions and formulations may include immunosuppressants, such as protein kinase inhibitors, including tyrosine kinase inhibitors (TKIs), in conjunction with various types of therapeutic nucleic acids (TNAs) and carriers (e.g., lipid nanoparticles).Type: ApplicationFiled: August 11, 2020Publication date: September 15, 2022Inventors: Sebastian Aguirre, Ching-Hung Chang, Debra Klatte
-
Publication number: 20220293561Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.Type: ApplicationFiled: March 12, 2021Publication date: September 15, 2022Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
-
Publication number: 20220102302Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.Type: ApplicationFiled: December 9, 2021Publication date: March 31, 2022Inventors: CHIANG-LIN SHIH, PEI-JHEN WU, CHING-HUNG CHANG, HSIH-YANG CHIU
-
Patent number: 11270962Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor component, a re-routing layer, a bonding dielectric and an insulating layer. The re-routing layer is disposed over the semiconductor component and electrically coupled to the semiconductor component. The bonding dielectric is disposed over the semiconductor component to surround a top portion of the re-routing layer. The insulating layer is disposed between the semiconductor component and the bonding dielectric to surround a bottom portion of the re-routing layer.Type: GrantFiled: October 28, 2019Date of Patent: March 8, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chiang-Lin Shih, Pei-Jhen Wu, Ching-Hung Chang, Hsih-Yang Chiu
-
Publication number: 20220059435Abstract: A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.Type: ApplicationFiled: November 3, 2021Publication date: February 24, 2022Inventors: Chiang-Lin SHIH, Hsih-Yang CHIU, Ching-Hung CHANG, Pei-Jhen WU
-
Patent number: 11217560Abstract: The present disclosure provides a die assembly. The die assembly includes a first die, a second die and a third die stacked together. The first die includes a plurality of first metal lines facing a plurality of second metal lines of the second die, and a second substrate beneath the second metal lines faces a plurality of third metal lines of the third die. The die assembly further includes at least one first plug, a first redistribution layer and a second redistribution layer. The first plug penetrates through the second substrate to connect to at least one of the second metal lines. A first redistribution layer physically connects at least one of the first metal lines to at least one of the second metal lines, and a second redistribution layer physically connects at least one of the third metal lines to the first plug.Type: GrantFiled: October 28, 2019Date of Patent: January 4, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chiang-Lin Shih, Pei-Jhen Wu, Ching-Hung Chang, Hsih-Yang Chiu
-
Patent number: 11205607Abstract: A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.Type: GrantFiled: January 9, 2020Date of Patent: December 21, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chiang-Lin Shih, Hsih-Yang Chiu, Ching-Hung Chang, Pei-Jhen Wu
-
Publication number: 20210217684Abstract: A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.Type: ApplicationFiled: January 9, 2020Publication date: July 15, 2021Inventors: Chiang-Lin SHIH, Hsih-Yang CHIU, Ching-Hung CHANG, Pei-Jhen WU
-
Patent number: 11063003Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor wafer, a plurality of semiconductor chips, and a plurality of first protection dams. The semiconductor wafer has a plurality of functional regions separated by a plurality of vertical streets and a plurality of horizontal streets. The semiconductor chips are mounted on the functional regions, respectively. The first protection dams are disposed on the vertical streets and the horizontal streets and spaced from the semiconductor chips. A height of the first protection dam is not less than a height of the semiconductor chip.Type: GrantFiled: October 2, 2018Date of Patent: July 13, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Hung Chang, Hsih-Yang Chiu
-
Publication number: 20210125947Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor component, a re-routing layer, a bonding dielectric and an insulating layer. The re-routing layer is disposed over the semiconductor component and electrically coupled to the semiconductor component. The bonding dielectric is disposed over the semiconductor component to surround a top portion of the re-routing layer. The insulating layer is disposed between the semiconductor component and the bonding dielectric to surround a bottom portion of the re-routing layer.Type: ApplicationFiled: October 28, 2019Publication date: April 29, 2021Inventors: Chiang-Lin SHIH, Pei-Jhen WU, Ching-Hung CHANG, Hsih-Yang CHIU
-
Publication number: 20210125966Abstract: The present disclosure provides a die assembly. The die assembly includes a first die, a second die and a third die stacked together. The first die includes a plurality of first metal lines facing a plurality of second metal lines of the second die, and a second substrate beneath the second metal lines faces a plurality of third metal lines of the third die. The die assembly further includes at least one first plug, a first redistribution layer and a second redistribution layer. The first plug penetrates through the second substrate to connect to at least one of the second metal lines. A first redistribution layer physically connects at least one of the first metal lines to at least one of the second metal lines, and a second redistribution layer physically connects at least one of the third metal lines to the first plug.Type: ApplicationFiled: October 28, 2019Publication date: April 29, 2021Inventors: Chiang-Lin SHIH, Pei-Jhen WU, Ching-Hung CHANG, Hsih-Yang CHIU
-
Patent number: 10910345Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second ILD layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of first metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second metal lines in the second ILD layer.Type: GrantFiled: May 2, 2019Date of Patent: February 2, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chiang-Lin Shih, Pei-Jhen Wu, Ching-Hung Chang, Hsih-Yang Chiu
-
Publication number: 20200357765Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: PEI-JHEN WU, HSIH-YANG CHIU, CHIANG-LIN SHIH, CHING-HUNG CHANG, YI-JEN LO
-
Publication number: 20200350284Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second ILD layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of first metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second metal lines in the second ILD layer.Type: ApplicationFiled: May 2, 2019Publication date: November 5, 2020Inventors: CHIANG-LIN SHIH, PEI-JHEN WU, CHING-HUNG CHANG, HSIH-YANG CHIU