Abstract: A bag is filled with liquid, instead of an airbag filled with gas, to deform a bottom wafer toward a top wafer during a wafer bonding process. As a result, the liquid is less susceptible to temperature changes, which reduces run-out variation across wafer bonding processes. Reducing run-out variation conserves wasted wafers by increasing yield and reducing a quantity of non-functioning devices that are produced. Additionally, in some implementations, the liquid may be pre-heated before the bag is filled with the liquid. As a result, the bottom wafer (and, to some extent, the top wafer) experiences some thermal deformation and less mechanical deformation, which further increases yield and reduces a quantity of non-functioning devices that are produced.

Abstract: Various embodiments of the present disclosure are directed towards a method. The method includes providing a first semiconductor workpiece and a second semiconductor workpiece onto a platform. A plurality of positioning structures move the second semiconductor workpiece over the first semiconductor workpiece while moving from a plurality of reference positions to a plurality of first positions. A bonding apparatus is operated to bond the second semiconductor workpiece to the first semiconductor workpiece. The positioning structures are moved from the plurality of reference positions to a plurality of second positions. The positioning structures physically contact an outer perimeter of the first semiconductor workpiece and/or an outer perimeter of the second semiconductor workpiece while at the plurality of second positions.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes performing a bonding process to bond a first semiconductor substrate to a second semiconductor substrate. A shift measurement process is performed on the first and second semiconductor substrates. The shift measurement process includes moving a plurality of substrate pins from a plurality of initial positions to a plurality of measurement positions. The plurality of substrate pins are disposed outside of perimeters of the first and second semiconductor substrates. A shift value is determined between the first semiconductor substrate and the second semiconductor substrate based at least in part on a difference between the plurality of initial positions and the plurality of measurement positions.

Abstract: Some implementations described herein provide a bonding tool having a top bonding fixture that includes an inflatable forcing structure (e.g., a gas bag). When pressurized, the inflatable forcing structure has a curved surface that protrudes from an under side of the top bonding fixture to deform a top semiconductor substrate during a bonding operation. A rate of inflation and/or a pressure within the inflatable forcing structure may be controlled to distribute a force more evenly in a bond region of the semiconductor substrate relative to another bonding tool having another top bonding fixture including a striker pin.

Abstract: Some implementations herein provide a semiconductor substrate including a multi-layer alignment mark structure and methods of formation. The multi-layer alignment mark structure may include concentric rings (e.g., a multi-ring bond mark structure) and a dummy pad structure below the concentric rings. For a light source of a given wavelength, the dummy pad structure may create an optical contrast between the concentric rings and annular regions of a dielectric region in which the concentric rings are formed. The optical contrast may improve a detectability of the multi-layer alignment mark structure by an automated optical inspection system relative to another alignment mark structure not including the dummy pad structure. The improved detectability, may in turn, reduce an amount of recognition errors by the automated optical inspection system detecting the multi-layer alignment mark structure to improve an efficiency of a semiconductor processing tool including the automated optical inspection system.

Abstract: Various embodiments of the present disclosure are directed towards a processing system including a bonding device. The bonding device is configured to perform a bonding process to bond a first semiconductor workpiece and a second semiconductor workpiece together. A shift detection device is configured to determine a shift value between the first semiconductor workpiece and the second semiconductor workpiece. One or more semiconductor processing devices are configured to form one or more layers and/or one or more structures in and/or on the second semiconductor workpiece. A controller is configured to adjust one or more parameters of at least one of the one or more semiconductor processing devices based at least in part on the shift value.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

Abstract: A secondary-side protection and sense circuit for a power converter has a sensing component, an adder amplifying circuit, an electronic switch, and a charge/discharge circuit. The sensing component is connected to an output connecting terminal of the power converter. The adder amplifying circuit has an operational amplifier, a first resistor, and a second resistor. The operational amplifier has an input terminal connected to the sensing component, an output terminal connected to a primary-side control component, and a power terminal. The first resistor and the second resistor are connected in series and between the input terminal and the power terminal of the operational amplifier. The electronic switch is connected between a ground terminal and a connection node between the first resistor and the second resistor. The charge/discharge circuit is connected to the electronic switch and the power terminal of the operational amplifier.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Abstract: A bag is filled with liquid, instead of an airbag filled with gas, to deform a bottom wafer toward a top wafer during a wafer bonding process. As a result, the liquid is less susceptible to temperature changes, which reduces run-out variation across wafer bonding processes. Reducing run-out variation conserves wasted wafers by increasing yield and reducing a quantity of non-functioning devices that are produced. Additionally, in some implementations, the liquid may be pre-heated before the bag is filled with the liquid. As a result, the bottom wafer (and, to some extent, the top wafer) experiences some thermal deformation and less mechanical deformation, which further increases yield and reduces a quantity of non-functioning devices that are produced.

Abstract: A secondary-side protection and sense circuit for a power converter has a sensing component, an adder amplifying circuit, an electronic switch, and a charge/discharge circuit. The sensing component is connected to an output connecting terminal of the power converter. The adder amplifying circuit has an operational amplifier, a first resistor, and a second resistor. The operational amplifier has an input terminal connected to the sensing component, an output terminal connected to a primary-side control component, and a power terminal. The first resistor and the second resistor are connected in series and between the input terminal and the power terminal of the operational amplifier. The electronic switch is connected between a ground terminal and a connection node between the first resistor and the second resistor. The charge/discharge circuit is connected to the electronic switch and the power terminal of the operational amplifier.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes performing a bonding process to bond a first semiconductor substrate to a second semiconductor substrate. A shift measurement process is performed on the first and second semiconductor substrates. The shift measurement process includes moving a plurality of substrate pins from a plurality of initial positions to a plurality of measurement positions. The plurality of substrate pins are disposed outside of perimeters of the first and second semiconductor substrates. A shift value is determined between the first semiconductor substrate and the second semiconductor substrate based at least in part on a difference between the plurality of initial positions and the plurality of measurement positions.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.