Patents by Inventor Ching-Hung Wang
Ching-Hung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969236Abstract: A wearable device for measuring blood pressure comprises a housing with through-holes formed thereon, a processing unit disposed in the housing, a display connected to the processing unit, a plurality of sensors connected to the processing unit, the sensors being configured to transmit at least one physiological signal to the processing unit via the through-holes, and a time delay structure connected between one of the through-holes and one of the sensors and configured to lengthen a path distance between the skin surface and the sensor, wherein the processing unit is configured to determine a systolic arterial pressure and a diastolic arterial pressure by the at least one physiological signal and a Moens-Korteweg (MK) function, and to control the display to display the systolic arterial pressure and the diastolic arterial pressure to be read by the user.Type: GrantFiled: May 24, 2019Date of Patent: April 30, 2024Assignee: Accurate Meditech IncInventors: Kuan Jen Wang, Cheng Yan Guo, Ching-Hung Huang
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Patent number: 11955881Abstract: A secondary-side protection and sense circuit for a power converter has a sensing component, an adder amplifying circuit, an electronic switch, and a charge/discharge circuit. The sensing component is connected to an output connecting terminal of the power converter. The adder amplifying circuit has an operational amplifier, a first resistor, and a second resistor. The operational amplifier has an input terminal connected to the sensing component, an output terminal connected to a primary-side control component, and a power terminal. The first resistor and the second resistor are connected in series and between the input terminal and the power terminal of the operational amplifier. The electronic switch is connected between a ground terminal and a connection node between the first resistor and the second resistor. The charge/discharge circuit is connected to the electronic switch and the power terminal of the operational amplifier.Type: GrantFiled: March 10, 2022Date of Patent: April 9, 2024Assignee: MINMAX TECHNOLOGY CO., LTDInventors: Ching-Hung Wang, Yu-Hsuan Chen
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Patent number: 11948798Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.Type: GrantFiled: July 16, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang, Tze-Liang Lee
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Publication number: 20240072082Abstract: A boron (B) layer may be formed as a passivation layer in a recess in which a vertical transfer gate is to be formed. The recess may then be filled with a gate electrode of the vertical transfer gate over the passivation layer (and/or one or more intervening layers) to form the vertical transfer gate. The passivation layer may be formed in the recess by epitaxial growth. The use of epitaxy to grow the passivation layer enables precise control over the profile, uniformity, and boron concentration in the passivation layer. Moreover, the use of epitaxy to grow the passivation layer may reduce the diffusion length of the passivation layer into the substrate of the pixel sensor, which provides increased area in the pixel sensor for the photodiode.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Yu-Hung CHENG, Tzu-Jui WANG, Ching I. LI
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Patent number: 11916022Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.Type: GrantFiled: June 7, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
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Publication number: 20230378125Abstract: A bag is filled with liquid, instead of an airbag filled with gas, to deform a bottom wafer toward a top wafer during a wafer bonding process. As a result, the liquid is less susceptible to temperature changes, which reduces run-out variation across wafer bonding processes. Reducing run-out variation conserves wasted wafers by increasing yield and reducing a quantity of non-functioning devices that are produced. Additionally, in some implementations, the liquid may be pre-heated before the bag is filled with the liquid. As a result, the bottom wafer (and, to some extent, the top wafer) experiences some thermal deformation and less mechanical deformation, which further increases yield and reduces a quantity of non-functioning devices that are produced.Type: ApplicationFiled: May 19, 2022Publication date: November 23, 2023Inventors: Tzu-Wei YU, Ching-Hung WANG, Yeong-Jyh LIN, Ching I LI
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Publication number: 20230291302Abstract: A secondary-side protection and sense circuit for a power converter has a sensing component, an adder amplifying circuit, an electronic switch, and a charge/discharge circuit. The sensing component is connected to an output connecting terminal of the power converter. The adder amplifying circuit has an operational amplifier, a first resistor, and a second resistor. The operational amplifier has an input terminal connected to the sensing component, an output terminal connected to a primary-side control component, and a power terminal. The first resistor and the second resistor are connected in series and between the input terminal and the power terminal of the operational amplifier. The electronic switch is connected between a ground terminal and a connection node between the first resistor and the second resistor. The charge/discharge circuit is connected to the electronic switch and the power terminal of the operational amplifier.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: CHING-HUNG WANG, YU-HSUAN CHEN
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Publication number: 20230282612Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes performing a bonding process to bond a first semiconductor substrate to a second semiconductor substrate. A shift measurement process is performed on the first and second semiconductor substrates. The shift measurement process includes moving a plurality of substrate pins from a plurality of initial positions to a plurality of measurement positions. The plurality of substrate pins are disposed outside of perimeters of the first and second semiconductor substrates. A shift value is determined between the first semiconductor substrate and the second semiconductor substrate based at least in part on a difference between the plurality of initial positions and the plurality of measurement positions.Type: ApplicationFiled: May 8, 2023Publication date: September 7, 2023Inventors: Ching-Hung Wang, Yeong-Jyh Lin, Ching I Li, Tzu-Wei Yu, Chung-Yi Yu
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Patent number: 11688717Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.Type: GrantFiled: August 26, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hung Wang, Yeong-Jyh Lin, Ching I Li, Tzu-Wei Yu, Chung-Yi Yu
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Publication number: 20230187359Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Patent number: 11610842Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.Type: GrantFiled: December 2, 2020Date of Patent: March 21, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20230066893Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Ching-Hung Wang, Yeong-Jyh Lin, Ching I Li, Tzu-Wei Yu, Chung-Yi Yu
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Publication number: 20220328419Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.Type: ApplicationFiled: June 7, 2022Publication date: October 13, 2022Inventors: Yeong-Jyh Lin, Ching I. Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
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Patent number: 11362038Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.Type: GrantFiled: October 5, 2020Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
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Publication number: 20220173040Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.Type: ApplicationFiled: December 2, 2020Publication date: June 2, 2022Applicant: MACRONIX International Co., Ltd.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20210375781Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.Type: ApplicationFiled: October 5, 2020Publication date: December 2, 2021Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
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Patent number: 11189515Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.Type: GrantFiled: March 25, 2020Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hung Wang, Ping-Yin Liu, Yeong-Jyh Lin, Yeur-Luen Tu
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Publication number: 20200227298Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.Type: ApplicationFiled: March 25, 2020Publication date: July 16, 2020Inventors: Ching-Hung Wang, Ping-Yin Liu, Yeong-Jyh Lin, Yeur-Luen Tu
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Patent number: 10636688Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.Type: GrantFiled: June 22, 2018Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hung Wang, Ping-Yin Liu, Yeong-Jyh Lin, Yeur-Luen Tu
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Publication number: 20190393067Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.Type: ApplicationFiled: June 22, 2018Publication date: December 26, 2019Inventors: Ching-Hung Wang, Ping-Yin Liu, Yeong-Jyh Lin, Yeur-Luen Tu