Patents by Inventor Ching-Hwan Su

Ching-Hwan Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7304728
    Abstract: A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: December 4, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Tzung Chang, Yu-Ku Lin, Shih-Ho Lin, Kei-Wei Chen, Ting-Chun Wang, Ching-Hwan Su, Ying-Lang Wang
  • Publication number: 20060055928
    Abstract: A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.
    Type: Application
    Filed: September 15, 2004
    Publication date: March 16, 2006
    Inventors: Shih-Tzung Chang, Yu-Ku Lin, Shih-Ho Lin, Kei-Wei Chen, Ting-Chun Wang, Ching-Hwan Su, Ying-Lang Wang
  • Publication number: 20050236181
    Abstract: A method for preventing the formation of voids and contaminants in vias during the fabrication of a metal interconnect structure such as a dual damascene structure is disclosed. The method includes providing a substrate; providing a dielectric layer having trench openings and via openings on the substrate, wherein the ratio of the sum of the areas of the trench openings to the sum of the areas of the via openings is between 1 and 300; wherein the via opening bottom has a width of less than about 25 ?m; and electroplating a metal in the trench openings and via openings. An interconnect structure having at least one void-free via is further disclosed.
    Type: Application
    Filed: August 12, 2004
    Publication date: October 27, 2005
    Inventors: Kei-Wei Chen, Shih-Ho Lin, Chun-Chang Chen, Ching-Hwan Su, Yu-Ku Lin, Ying-Lang Wang, De-Dui Liao, Meng-Chao Tzeng