Patents by Inventor Ching-Ju Chen
Ching-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250053211Abstract: A system comprises a controller, configured to receive at least one thermal control setting and a system temperature, and to perform a first thermal throttling operation according to at least one thermal control instruction; and an application, coupled to the controller, configured to receive the at least one thermal control setting and the system temperature from the controller, and to generate the at least one thermal control instruction according to the at least one thermal control setting and the system temperature.Type: ApplicationFiled: August 8, 2023Publication date: February 13, 2025Applicant: MEDIATEK INC.Inventors: Hsien-Hsi Hsieh, Ching-Yeh Chen, Yu-Ming Lin, Hsing-Ju Wei
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Patent number: 12225735Abstract: A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.Type: GrantFiled: June 7, 2022Date of Patent: February 11, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ju Li, Kuo-Pin Chang, Yu-Wei Ting, Ching-En Chen, Kuo-Ching Huang
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Patent number: 12211823Abstract: A package structure includes first and second dies, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die electrically bonded to the first die includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a first barrier layer and a conductive layer on the first barrier layer. The through substrate via is electrically connected to the redistribution layer, and the conductive layer is in contact with a conductive post of the through via and separated from the through substrate via by the first barrier layer therebetween.Type: GrantFiled: May 9, 2022Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
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Patent number: 12040261Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: GrantFiled: March 29, 2022Date of Patent: July 16, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Tsung-Tang Tsai, Huang-Hsien Chang, Ching-Ju Chen
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Patent number: 11894340Abstract: A package structure includes a wiring structure and a first electronic device. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The first electronic device is electrically connected to the wiring structure, and has a first surface, a second surface and at least one lateral side surface extending between the first surface and the second surface. The first electronic device includes a first active circuit region and a first protrusion portion. The first protrusion portion protrudes from the at least one lateral side surface of the first electronic device. A portion of the first active circuit region is disposed in the first protrusion portion.Type: GrantFiled: November 15, 2019Date of Patent: February 6, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Min Lung Huang, Huang-Hsien Chang, Tsung-Tang Tsai, Ching-Ju Chen
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Publication number: 20240021540Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.Type: ApplicationFiled: August 15, 2023Publication date: January 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Min Lung HUANG, Huang-Hsien CHANG, Tsung-Tang TSAI, Ching-Ju CHEN
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Patent number: 11728282Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.Type: GrantFiled: October 17, 2019Date of Patent: August 15, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Min Lung Huang, Huang-Hsien Chang, Tsung-Tang Tsai, Ching-Ju Chen
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Patent number: 11608170Abstract: A buoy position monitoring method includes a buoy positioning step, an unmanned aerial vehicle receiving step and an unmanned aerial vehicle flying step. In the buoy positioning step, a plurality of buoys are put on a water surface. Each of the buoys is capable of sending a detecting signal. Each of the detecting signals is sent periodically and includes a position dataset of each of the buoys. In the unmanned aerial vehicle receiving step, an unmanned aerial vehicle is disposed on an initial position, and the unmanned aerial vehicle receives the detecting signals. In the unmanned aerial vehicle flying step, when at least one of the buoys is lost, the unmanned aerial vehicle flies to a predetermined position to get contact with the at least one buoy that is lost.Type: GrantFiled: April 9, 2020Date of Patent: March 21, 2023Assignee: NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Ching-Ju Chen, Chuan-Yu Chang, Chia-Yan Cheng, Meng-Syue Li, Yueh-Min Huang
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Publication number: 20230027674Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.Type: ApplicationFiled: September 30, 2022Publication date: January 26, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jhao-Cheng CHEN, Huang-Hsien CHANG, Wen-Long LU, Shao Hsuan CHUANG, Ching-Ju CHEN, Tse-Chuan CHOU
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Patent number: 11495557Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.Type: GrantFiled: March 20, 2020Date of Patent: November 8, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jhao-Cheng Chen, Huang-Hsien Chang, Wen-Long Lu, Shao Hsuan Chuang, Ching-Ju Chen, Tse-Chuan Chou
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Publication number: 20220223507Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Tsung-Tang TSAI, Huang-Hsien CHANG, Ching-Ju CHEN
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Patent number: 11289411Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: GrantFiled: July 29, 2020Date of Patent: March 29, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Tsung-Tang Tsai, Huang-Hsien Chang, Ching-Ju Chen
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Publication number: 20210296267Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.Type: ApplicationFiled: March 20, 2020Publication date: September 23, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jhao-Cheng CHEN, Huang-Hsien CHANG, Wen-Long LU, Shao Hsuan CHUANG, Ching-Ju CHEN, Tse-Chuan CHOU
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Publication number: 20210233836Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: ApplicationFiled: July 29, 2020Publication date: July 29, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Tsung-Tang TSAI, Huang-Hsien CHANG, Ching-Ju CHEN
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Publication number: 20210151407Abstract: A package structure includes a wiring structure and a first electronic device. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The first electronic device is electrically connected to the wiring structure, and has a first surface, a second surface and at least one lateral side surface extending between the first surface and the second surface. The first electronic device includes a first active circuit region and a first protrusion portion. The first protrusion portion protrudes from the at least one lateral side surface of the first electronic device. A portion of the first active circuit region is disposed in the first protrusion portion.Type: ApplicationFiled: November 15, 2019Publication date: May 20, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Min Lung HUANG, Huang-Hsien CHANG, Tsung-Tang TSAI, Ching-Ju CHEN
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Publication number: 20210118812Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Min Lung HUANG, Huang-Hsien CHANG, Tsung-Tang TSAI, Ching-Ju CHEN
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Publication number: 20200324897Abstract: A buoy position monitoring method includes a buoy positioning step, an unmanned aerial vehicle receiving step and an unmanned aerial vehicle flying step. In the buoy positioning step, a plurality of buoys are put on a water surface. Each of the buoys is capable of sending a detecting signal. Each of the detecting signals is sent periodically and includes a position dataset of each of the buoys. In the unmanned aerial vehicle receiving step, an unmanned aerial vehicle is disposed on an initial position, and the unmanned aerial vehicle receives the detecting signals. In the unmanned aerial vehicle flying step, when at least one of the buoys is lost, the unmanned aerial vehicle flies to a predetermined position to get contact with the at least one buoy that is lost.Type: ApplicationFiled: April 9, 2020Publication date: October 15, 2020Inventors: Ching-Ju CHEN, Chuan-Yu CHANG, Chia-Yan CHENG, Meng-Syue LI
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Patent number: 10741483Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: GrantFiled: January 28, 2020Date of Patent: August 11, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Tsung-Tang Tsai, Huang-Hsien Chang, Ching-Ju Chen