Abstract: A method of noise mitigation in a multi-carrier communication system includes receiving a signal from a decision device, determining whether synchronization symbol update is enabled, updating at least one of frequency-domain equalizer (FEQ) coefficients or digital echo canceller (DEC) coefficients in synchronization symbol periods if the synchronization symbol update is enabled, determining whether data symbol update is performed if the synchronization symbol update is not enabled, determining whether a flag associated with the signal is set if the data symbol update is not performed, and updating at least one of FEQ or DEC coefficients associated with the signal in synchronization symbol periods if the flag is set.

Abstract: A collision detection method for a multiple access communication system is disclosed. By using the error term of a time-domain equalized signal as a detection source, an operation on the error term can be performed to determine whether collision occurs. For example, the mean square error and/or maximum value of the real part and/or imaginary part of the error term can be calculated or selected to distinguish the collision and non-collision situations. A collision detection apparatus for a multiple access communication system is also disclosed. The collision detection apparatus utilizes an existent adaptive equalizer and signal processing device for obtaining received information data bits to obtain the error term. The error term is further processed by a mean-square-error or maximum-absolute-value operator to determine the collision status.

Abstract: A differential phase discriminator includes a phase compensation circuit to compensate for timing drift and error for recovering timing information in a digital phase lock loop. The differential phase discriminator uses a differential phase detector to compute the phase difference of two consecutive frequency domain signal samples. The phase compensation circuit determines a phase correction term by computing the difference between the absolute values of the real and imaginary parts of a frequency domain signal sample. A weighting factor is computed by adjusting the sum of the absolute values of the real and imaginary parts of the frequency domain signal sample with a ratio adjustment factor. A phase compensation value is then computed by multiplying the phase correction term by the weighting factor. The phase compensation value is added to the uncorrected output of the differential phase detector.

Abstract: A method and an apparatus are provided in this invention to select an optimal swapping technique in discrete multi-tone system. The algorithm for performing gain-swapping is also proposed in the present invention. A swapping technique is selected from gain-swapping and a combination of bit-swapping and gain-swapping based on two index values such that the difference between the maximum mean square error (MSEmax) and the minimum mean square error (MSEmin) is minimized and the gain factor constraints are met. The first index value I is representative of range of improvement when adopting the gain-swapping as the swapping technique, and the second index value J is representative of range of improvement when adopting a combination of the gain-swapping and the bit-swapping as the swapping technique.

Abstract: An equalizing device includes a first filter, a target filter, an error determining device coupled with the first filter and the target filter, and a coefficient processor coupled with the error determining device. The first filter has a first set of coefficients and processes input signals transmitted through a communication channel to reduce channel response. The target filter has a second set of coefficients and generates a target channel output. The error determining device then processes an output of the first filter and the target channel output to generate error signals. The coefficient processor maintains constant at least one coefficient of the first or the second sets of coefficients and updates the remaining coefficients of the first and the second sets of coefficients based on the error signals.

Abstract: Architecture of an efficient adaptive digital echo canceller includes a frequency domain update block, a far-end signal estimation block and a time domain echo cancellation block. The echo canceller has a training mode in which the frequency domain update block and far-end signal estimation block are first trained to estimate the echo channel and target channel. After the training mode, the time domain echo cancellation block uses the estimated echo channel to synthesize an echo replica and subtracted it from the received signal continuously before or in an operation mode. When a synchronization frame is received in the operation mode, the frequency domain update block and the far-end signal estimation block are used to retune both echo channel and target channel for improving system performance.

Abstract: A receiver in a home phone-lines local area network system is proposed. The receiver can distinguish a valid signal and a collision backoff signal from noises in real time. The receiver for a home phone-lines LAN system comprises a QAM demodulator, an equalizer, a deconstellation, and a transmission data reading device. The receiver further comprises a signal match filter module and a detector. The signal match filter module comprises an adder and at least a cross-correlator. The adder adds the “I” signal and “Q” signal outputted from the QAM demodulator and outputs a combined signal. The cross-correlator performs match operation, such as a comparison operation or a correlation operation, of the combined signal and an identification value and outputs a match value to the detector. Since the signal match filter module connects directly to the output of QAM demodulator, it can immediately identify the identification code TRN16 contained in the received signal.

Abstract: An apparatus is adapted for interleaving an incoming stream of data blocks, each of which has a predetermined number (N) of block units indexed consecutively from 0 to (N−1), The interleaving is accomplished at a predetermined interleaving depth (D). A first one of the block units has no delay associated therewith, and subsequent ones of the block units in a designated one of the data blocks have a delay equal to (D−1) more than an immediately preceding one of the block units in the designated one of the data blocks. The apparatus includes a data buffer configured to have a number of lines equal to (N−1), an output unit, and a control unit. Each of the lines has a size sufficient to accommodate a predetermined number of the block units. The output unit outputs one of the block units of the incoming stream directly when the delay associated therewith is equal to zero.

Abstract: A digital-to-analog converting method operating under two clock signals of different periods is disclosed. The method includes steps of monitoring a phase relationship between the two clock signals; starting transmission of a plurality of pre-stored series of waveform samples in response to each rising edge of the first clock signal, wherein a phase difference is present between every two adjacent series of waveform samples; outputting the waveform samples of each series in response to rising edges of the second clock signal; and selecting one of the plurality of pre-stored sets of waveform samples to be converted into an analog signal according to the phase relationship. The various pre-stored series of waveform samples having therebetween phase differences are optionally used for phase compensation so as to reduce the clock jitter between the two clock signals. A digital-to-analog converter for implementing the above-mentioned method is also disclosed.

Abstract: A differential phase discriminator includes a phase compensation circuit to compensate for timing drift and error for recovering timing information in a digital phase lock loop. The differential phase discriminator uses a differential phase detector to compute the phase difference of two consecutive frequency domain signal samples. The phase compensation circuit determines a phase correction term by computing the difference between the absolute values of the real and imaginary parts of a frequency domain signal sample. A weighting factor is computed by adjusting the sum of the absolute values of the real and imaginary parts of the frequency domain signal sample with a ratio adjustment factor. A phase compensation value is then computed by multiplying the phase correction term by the weighting factor. The phase compensation value is added to the uncorrected output of the differential phase detector.

Abstract: A collision detection method for a multiple access communication system is disclosed. By using the error term of a time-domain equalized signal as a detection source, an operation on the error term can be performed to determine whether collision occurs. For example, the mean square error and/or maximum value of the real part and/or imaginary part of the error term can be calculated or selected to distinguish the collision and non-collision situations. A collision detection apparatus for a multiple access communication system is also disclosed. The collision detection apparatus utilizes an existent adaptive equalizer and signal processing device for obtaining received information data bits to obtain the error term. The error term is further processed by a mean-square-error or maximum-absolute-value operator to determine the collision status.

Abstract: A method and an apparatus are provided in this invention to select an optimal swapping technique in discrete multi-tone system. The algorithm for performing gain-swapping is also proposed in the present invention. A swapping technique is selected from gain-swapping and a combination of bit-swapping and gain-swapping based on two index values such that the difference between the maximum mean square error (MSEmax) and the minimum mean square error (MSEmin) is minimized and the gain factor constraints are met. The first index value I is representative of range of improvement when adopting the gain-swapping as the swapping technique, and the second index value J is representative of range of improvement when adopting a combination of the gain-swapping and the bit-swapping as the swapping technique.

Abstract: A DSSS receiver for processing a complex spread-spectrum signal which contains source information, the receiver including a despreading circuit which despreads a first complex signal that is derived from the spread-spectrum signal to produce a second complex signal; a differential demodulator which differentially demodulates the second complex signal to generate a third complex signal; and a sum and dump circuit which during each of successive symbol periods of the third complex signal sums multiple samples of the third complex signal to produce a fourth complex signal, wherein decision processing is performed in the fourth complex signal to extract the source information.