Patents by Inventor Ching-Kai Lin
Ching-Kai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11985765Abstract: A power adapter includes a circuit board, an electromagnetic interference filter, a shielding element, a power factor correction (PFC) inductor, a transformer and heating elements. The circuit board has a front side and a back side corresponding to each other, and a first long side and a second long side parallel to each other. The front side of the circuit board is divided into a first region, a second region and a third region along an extending direction of the first long side. The electromagnetic interference filter is disposed in the first region and close to the first long side. The shielding element is disposed in the first region and close to the electromagnetic interference filter. The PFC inductor is disposed in the first region of the circuit board and close to the second long side. The PFC inductor has a first long axis. The transformer is disposed in the third region and close to the first long side.Type: GrantFiled: July 29, 2022Date of Patent: May 14, 2024Assignee: FSP TECHNOLOGY INC.Inventors: Che-Min Lin, Chia-Hua Liu, Ching-Kai Lin
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Publication number: 20230108785Abstract: A power adapter includes a circuit board, an electromagnetic interference filter, a shielding element, a power factor correction (PFC) inductor, a transformer and heating elements. The circuit board has a front side and a back side corresponding to each other, and a first long side and a second long side parallel to each other. The front side of the circuit board is divided into a first region, a second region and a third region along an extending direction of the first long side. The electromagnetic interference filter is disposed in the first region and close to the first long side. The shielding element is disposed in the first region and close to the electromagnetic interference filter. The PFC inductor is disposed in the first region of the circuit board and close to the second long side. The PFC inductor has a first long axis. The transformer is disposed in the third region and close to the first long side.Type: ApplicationFiled: July 29, 2022Publication date: April 6, 2023Applicant: FSP TECHNOLOGY INC.Inventors: Che-Min Lin, Chia-Hua Liu, Ching-Kai Lin
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Patent number: 10644118Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: June 14, 2017Date of Patent: May 5, 2020Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
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Publication number: 20170288028Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: ApplicationFiled: June 14, 2017Publication date: October 5, 2017Inventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
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Patent number: 9691863Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: April 8, 2015Date of Patent: June 27, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
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Publication number: 20160300917Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: ApplicationFiled: April 8, 2015Publication date: October 13, 2016Inventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
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Patent number: 8420208Abstract: A method of forming a high-k dielectric material including forming at least two portions of titanium dioxide, the at least two portions of titanium dioxide comprising a first portion comprising amorphous titanium dioxide and a second portion comprising rutile titanium dioxide. A method of forming a high-k dielectric material including forming a first portion of titanium dioxide at a temperature of from about 150° C. to about 350° C. and forming a second portion of titanium dioxide at a temperature of from about 350° C. to about 600° C. A high-k dielectric material is also disclosed.Type: GrantFiled: August 11, 2010Date of Patent: April 16, 2013Assignee: Micron Technology, Inc.Inventors: Tsai-Yu Huang, Ching-Kai Lin
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Patent number: 8222163Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.Type: GrantFiled: August 6, 2010Date of Patent: July 17, 2012Assignee: Nanya Technology Corp.Inventors: Chao-Wen Lay, Ching-Kai Lin
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Publication number: 20120040162Abstract: A method of forming a high-k dielectric material including forming at least two portions of titanium dioxide, the at least two portions of titanium dioxide comprising a first portion comprising amorphous titanium dioxide and a second portion comprising rutile titanium dioxide. A method of forming a high-k dielectric material including forming a first portion of titanium dioxide at a temperature of from about 150° C. to about 350° C. and forming a second portion of titanium dioxide at a temperature of from about 350° C. to about 600° C. A high-k dielectric material is also disclosed.Type: ApplicationFiled: August 11, 2010Publication date: February 16, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Tsai-Yu Huang, Ching-Kai Lin
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Publication number: 20120034791Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.Type: ApplicationFiled: August 6, 2010Publication date: February 9, 2012Inventors: Chao-Wen Lay, Ching-Kai Lin
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Patent number: 6183940Abstract: A method of retaining the integrity of a photoresist pattern is provided where the patterned photoresist is treated prior to etching the principle layer. The pre-etch treatment encompasses a plasma treatment. In some embodiments employing an anti-reflective coating (ARC) layer, an isolation/protective layer is used to isolate the ARC from the photoresist. In some embodiments, the pre-etch treatment, advantageously provides for patterning the isolation/protection layer.Type: GrantFiled: March 17, 1998Date of Patent: February 6, 2001Assignee: Integrated Device Technology, Inc.Inventors: Chen-Yu Wang, Tseng You Syau, Ching-Kai Lin
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Patent number: D1044721Type: GrantFiled: February 16, 2023Date of Patent: October 1, 2024Assignee: FSP TECHNOLOGY INC.Inventors: Che-Min Lin, Chia-Hua Liu, Ching-Kai Lin
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Patent number: D1044722Type: GrantFiled: February 16, 2023Date of Patent: October 1, 2024Assignee: FSP TECHNOLOGY INC.Inventors: Che-Min Lin, Chia-Hua Liu, Ching-Kai Lin