Patents by Inventor Ching-Kai Lin

Ching-Kai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985765
    Abstract: A power adapter includes a circuit board, an electromagnetic interference filter, a shielding element, a power factor correction (PFC) inductor, a transformer and heating elements. The circuit board has a front side and a back side corresponding to each other, and a first long side and a second long side parallel to each other. The front side of the circuit board is divided into a first region, a second region and a third region along an extending direction of the first long side. The electromagnetic interference filter is disposed in the first region and close to the first long side. The shielding element is disposed in the first region and close to the electromagnetic interference filter. The PFC inductor is disposed in the first region of the circuit board and close to the second long side. The PFC inductor has a first long axis. The transformer is disposed in the third region and close to the first long side.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 14, 2024
    Assignee: FSP TECHNOLOGY INC.
    Inventors: Che-Min Lin, Chia-Hua Liu, Ching-Kai Lin
  • Publication number: 20230108785
    Abstract: A power adapter includes a circuit board, an electromagnetic interference filter, a shielding element, a power factor correction (PFC) inductor, a transformer and heating elements. The circuit board has a front side and a back side corresponding to each other, and a first long side and a second long side parallel to each other. The front side of the circuit board is divided into a first region, a second region and a third region along an extending direction of the first long side. The electromagnetic interference filter is disposed in the first region and close to the first long side. The shielding element is disposed in the first region and close to the electromagnetic interference filter. The PFC inductor is disposed in the first region of the circuit board and close to the second long side. The PFC inductor has a first long axis. The transformer is disposed in the third region and close to the first long side.
    Type: Application
    Filed: July 29, 2022
    Publication date: April 6, 2023
    Applicant: FSP TECHNOLOGY INC.
    Inventors: Che-Min Lin, Chia-Hua Liu, Ching-Kai Lin
  • Patent number: 10644118
    Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 5, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
  • Publication number: 20170288028
    Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 5, 2017
    Inventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
  • Patent number: 9691863
    Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 27, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
  • Publication number: 20160300917
    Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 13, 2016
    Inventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
  • Patent number: 8420208
    Abstract: A method of forming a high-k dielectric material including forming at least two portions of titanium dioxide, the at least two portions of titanium dioxide comprising a first portion comprising amorphous titanium dioxide and a second portion comprising rutile titanium dioxide. A method of forming a high-k dielectric material including forming a first portion of titanium dioxide at a temperature of from about 150° C. to about 350° C. and forming a second portion of titanium dioxide at a temperature of from about 350° C. to about 600° C. A high-k dielectric material is also disclosed.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: April 16, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Ching-Kai Lin
  • Patent number: 8222163
    Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: July 17, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Chao-Wen Lay, Ching-Kai Lin
  • Publication number: 20120040162
    Abstract: A method of forming a high-k dielectric material including forming at least two portions of titanium dioxide, the at least two portions of titanium dioxide comprising a first portion comprising amorphous titanium dioxide and a second portion comprising rutile titanium dioxide. A method of forming a high-k dielectric material including forming a first portion of titanium dioxide at a temperature of from about 150° C. to about 350° C. and forming a second portion of titanium dioxide at a temperature of from about 350° C. to about 600° C. A high-k dielectric material is also disclosed.
    Type: Application
    Filed: August 11, 2010
    Publication date: February 16, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tsai-Yu Huang, Ching-Kai Lin
  • Publication number: 20120034791
    Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Inventors: Chao-Wen Lay, Ching-Kai Lin
  • Patent number: 6183940
    Abstract: A method of retaining the integrity of a photoresist pattern is provided where the patterned photoresist is treated prior to etching the principle layer. The pre-etch treatment encompasses a plasma treatment. In some embodiments employing an anti-reflective coating (ARC) layer, an isolation/protective layer is used to isolate the ARC from the photoresist. In some embodiments, the pre-etch treatment, advantageously provides for patterning the isolation/protection layer.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: February 6, 2001
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chen-Yu Wang, Tseng You Syau, Ching-Kai Lin
  • Patent number: D1044721
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: October 1, 2024
    Assignee: FSP TECHNOLOGY INC.
    Inventors: Che-Min Lin, Chia-Hua Liu, Ching-Kai Lin
  • Patent number: D1044722
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: October 1, 2024
    Assignee: FSP TECHNOLOGY INC.
    Inventors: Che-Min Lin, Chia-Hua Liu, Ching-Kai Lin