Patents by Inventor Ching-Kang Chiu

Ching-Kang Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11335691
    Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: May 17, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
  • Publication number: 20210175237
    Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
  • Patent number: 10971501
    Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 6, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
  • Publication number: 20200328215
    Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.
    Type: Application
    Filed: May 29, 2019
    Publication date: October 15, 2020
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho