Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.

Abstract: An electrical connector for network cables includes a shell internally defining a first and a second insertion space communicable with each other via passages; conducting elements respectively including a conducting section seated in one passage and a first and a second contacting section extended from two opposite ends of the conducting section to extend into the first and the second insertion space, respectively; and a first and a second locating member mounted in the first and the second insertion space, respectively. The first and second locating members include a plurality of first and second guide slots, respectively, for receiving a partial length of the first and second contacting sections, respectively, such that the first and second contacting sections being pushed by inserted network cables are limited to move vertically in the first and second guide slots and accordingly firmly hold front ends of the network cables in the electrical connector.

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.

Abstract: An electrical connector for coaxial conductor includes a shell, a first cap, a second cap, a conducting member and a conductor. The first cap and the second cap are in contact with each other and simultaneously located in the shell. The conducting member has an end pressing against the first cap and another end against the second cap. The conductor is extended through the second cap, such that a section of the conductor that is projected into the second cap is connected to the conducting member. With the shell, the first cap, the second cap, the conducting member and the conductor assembled in the above manner, the number of parts for the electrical connector is decreased to enable a reduced overall volume of the electrical connector.

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.

Abstract: An electrical connector includes a housing internally defining a receiving passage having a front installation hole and a rear stop hole; an inner cap assembled to an inner side of the stop hole and internally defining a mounting passage; a pad assembled to an inner side of the installation hole and internally defining a holding passage; a conductor extended through and held in the holding passage with a forward exposed conducting pin section; and a flat spring member having a rear abutting end mounted in the mounting passage and a front clamping end riveted to a rear end of the conductor and forward pressed against a rear end surface of the pad, such that a spacing chamber is defined between an inner wall surface of the housing and the flat spring member. Therefore, the electrical conductor has fewer parts than conventional electrical connectors to enable reduced assembling complexity and time.

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.

Abstract: An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different.

Abstract: Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms.

Abstract: A coaxial connector device includes a connector bank with closely arranged installation connectors; a male connector including a screw-on section defining a first circumferential surface of a first outer diameter, a cable receiving section defining a second circumferential surface of a second outer diameter, and a tightening section axially located between the screw-on and the cable receiving section; a cable having an end extended through the male connector to electrically connect to one of the installation connectors; and a female connector connected to another end of the cable. The tightening section defines multiple grip sides, which are respectively located tangentially relative to the second circumferential surface with two lateral edges flush with the first circumferential surface, giving the tightening section a reduced size.

Abstract: Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms.

Abstract: Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms.

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

Abstract: Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms.

Abstract: A terminal load includes an insulating cylinder internally defining a receiving space having a locating surface, and having a front open end and a rear end provided with a notch; an insulating cap mounted to the front open end of the insulating cylinder; a circuit board mounted on the locating surface to rearwardly project a rear narrowed section from the notch; a connection terminal electrically connected with the circuit board to forward extend through the insulating cap; and a conductive cap having a top hole and fitted around the rear end of the insulating cylinder with the rear narrowed section of the circuit board extended through the top hole and clamped between two contacting arms at two opposite sides of the top hole. The terminal load with the above structure can be driven by punching to safely assemble to an outer housing, and the conductive cap ensures good conducting effect.

Abstract: A terminal load includes an insulating cylinder internally defining a receiving space having a locating surface, and having a front open end and a rear end provided with a notch; an insulating cap mounted to the front open end of the insulating cylinder; a circuit board mounted on the locating surface to rearwardly project a rear narrowed section from the notch; a connection terminal electrically connected with the circuit board to forward extend through the insulating cap; and a conductive cap having a top hole and fitted around the rear end of the insulating cylinder with the rear narrowed section of the circuit board extended through the top hole and clamped between two contacting arms at two opposite sides of the top hole. The terminal load with the above structure can be driven by punching to safely assemble to an outer housing, and the conductive cap ensures good conducting effect.

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

Abstract: An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different.