Patents by Inventor Ching Lang Yen

Ching Lang Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7339253
    Abstract: Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon substrate, and forming a layer of silicon oxide on the walls of the trench by thermal oxidation, such that the trench is sealed and a space is formed within the layer of silicon oxide. The space can contain a vacuum or any of a variety of gases depending upon conditions of the thermal oxidation step. Retrograde trench isolation structures containing a space are also provided.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: March 4, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chao-Tzung Tsai, Ling-Sung Wang, Ching Lang Yen
  • Patent number: 6926590
    Abstract: A method of improving the yield and performance of IC devices fabricated on a semiconductor wafer is disclosed. The method includes fabricating via plugs in via openings provided in an intermetal dielectric (IMD) layer on a wafer, subjecting the wafer to CMP to isolate the via plugs, immersing and soaking the wafer in deionized (DI) water, and drying the wafer using isopropyl alcohol, typically in a Marangoni-type dryer. The Marangoni IPA drying step prevents the formation of static electricity on the wafer, and thus, prevents the adherence of small charged particles to the wafer. As a result, the yield of IC devices fabricated on the wafer, as well as the performance of the devices, is enhanced.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: August 9, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo Hui Chang, Shing Long Lee, Ching Lang Yen
  • Patent number: 6261921
    Abstract: A method of forming a shallow trench isolation structure is described. A mask layer and a photoresist layer with an opening are formed on a substrate in sequence. The photoresist layer serves as an etching mask, and then a portion of the mask layer and a portion of the substrate are etched to form a trench in the substrate. A portion of the photoresist layer is removed, and the opening is in-situ widened. Then, a portion of the mask layer exposed by the widened opening is removed. In addition, a top corner of the trench is rounded after removing the portion of the mask layer. Finally, the trench is filled with an insulation material to form a shallow trench isolation structure.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: July 17, 2001
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Lang Yen, Chingfu Lin