Patents by Inventor Ching Li

Ching Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250012830
    Abstract: An adapter bracket includes a holder and a fixing element. The holder includes a first strip-shaped body and a second strip-shaped body. The first strip-shaped body is formed with a plurality of first notches linearly arranged on a first coupling surface of the first strip-shaped body. The second strip-shaped body is formed with a plurality of second notches linearly arranged on a second coupling surface of the second strip-shaped body. The fixing element detachably couples the first strip-shaped body and the second strip-shaped body together, so that the first coupling surface and the second coupling surface are in contact with each other, and the first notches and the second notches are jointly combined into a plurality of fastening holes arranged linearly, and each of the fastening holes can hold an object therein.
    Type: Application
    Filed: April 17, 2024
    Publication date: January 9, 2025
    Inventors: Ching-Li LIN, Kao-Shan YANG
  • Publication number: 20240393187
    Abstract: An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.
    Type: Application
    Filed: July 8, 2024
    Publication date: November 28, 2024
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Ming HU, Chung-Kuang CHEN, Chia-Ching LI, Chien-Fu HUANG
  • Publication number: 20240370379
    Abstract: An electronic device includes a memory usage identification circuit and a system-level cache (SLC). The memory usage identification circuit obtains a memory usage indicator that depends on memory usage of a storage space allocated in a system memory at which memory access is requested by a physical address. The SLC includes a cache memory and a cache controller. The cache controller performs cache management upon the cache memory according to the physical address and the memory usage indicator.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chun-Ming Su, Chih-Wei Hung, Yi-Lun Lin, Kun-Lung Chen, Po-Han Wang, Ming-Hung Hsieh, Yun-Ching Li
  • Patent number: 12076677
    Abstract: A method for collecting dust from a single crystal growth system includes providing dry air and oxygen into an exit pipe connecting to the single crystal growth system, blowing a first inert gas into the exit pipe to compel the dust oxide toward a dust collecting device, collecting the dust oxide by the dust collecting device; and providing a rotary pump to transport residues of the dust oxide backward. The oxygen reacts with the unstable dust for forming dust oxide. The exit pipe is used to exhaust unstable dust from the single crystal growth system.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: September 3, 2024
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Masami Nakanishi, Yu-Sheng Su, I-Ching Li
  • Patent number: 12061125
    Abstract: An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 13, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Ming Hu, Chung-Kuang Chen, Chia-Ching Li, Chien-Fu Huang
  • Patent number: 12056949
    Abstract: Techniques are disclosed for detecting an uncovered portion of a body of a person in a frame of video content. In an example, a first machine learning model of a computing system may output a first score for the frame based on a map that identifies a region of the frame associated with an uncovered body part type. Depending on a value of the first score, a second machine learning model that includes a neural network architecture may further analyze the frame to output a second score. The first score and second score may be merged to produce a third score for the frame. A plurality of scores may be determined, respectively, for frames of the video content, and a maximum score may be selected. The video content may be selected for presentation on a display for further evaluation based on the maximum score.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: August 6, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Xiaohang Sun, Mohamed Kamal Omar, Alexander Ratnikov, Ahmed Aly Saad Ahmed, Tai-Ching Li, Travis Silvers, Hanxiao Deng, Muhammad Raffay Hamid, Ivan Ryndin
  • Patent number: 12044631
    Abstract: A wafer surface defect inspection method and a wafer surface defect inspection apparatus are provided. The method includes the following steps. Scanning information of a wafer is received, and the scanning information includes multiple scanning parameters. At least one reference point of the scanning information is determined, and path information is generated according to the at least one reference point and a reference value. Multiple first scanning parameters corresponding to the path information in the scanning parameters are obtained according to the path information to generate a curve chart. According to the curve chart, it is determined whether the wafer has a defect, and a defect type of the defect is determined.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: July 23, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Shang-Chi Wang, Miao-Pei Chen, Han-Zong Wu, Chia-Chi Tsai, I-Ching Li
  • Patent number: 11986792
    Abstract: The present invention provides a photocuring device, comprising a housing and an ultraviolet (UV) light module, wherein the housing comprises an electroluminescent layer and/or a touch layer and a control module connected to the electroluminescent layer and/or the touch layer by an electrical means. The photocuring device of the invention not only features a low material cost and low production cost, but also allows its display interface and/or operation interface to be provided at any position of the housing of the photocuring device, without limitations in size, shape, or angle. Furthermore, the photocuring device of the invention allows its display interface and/or operation interface to be simplified as needed to facilitate operation and viewing by a manicurist or one who is receiving a manicure.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: May 21, 2024
    Assignee: COSMEX CO., LTD.
    Inventors: Wan-Chieh Hsieh, Ya-Wen Wu, Yu-Ching Li, Wen-Shan Chung
  • Patent number: 11928880
    Abstract: Techniques are disclosed for detecting an uncovered portion of a body of a person in a frame of video content. In an example, a first machine learning model of a computing system may output a first score for the frame based on a map that identifies a region of the frame associated with an uncovered body part type. Depending on a value of the first score, a second machine learning model that includes a neural network architecture may further analyze the frame to output a second score. The first score and second score may be merged to produce a third score for the frame. A plurality of scores may be determined, respectively, for frames of the video content, and a maximum score may be selected. The video content may be selected for presentation on a display for further evaluation based on the maximum score.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: March 12, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Xiaohang Sun, Mohamed Kamal Omar, Alexander Ratnikov, Ahmed Aly Saad Ahmed, Tai-Ching Li, Travis Silvers, Hanxiao Deng, Muhammad Raffay Hamid, Ivan Ryndin
  • Publication number: 20240075558
    Abstract: A processing method of a single crystal material includes the following steps. A single crystal material is provided as an object to be modified. The amorphous phase modification apparatus is used for emitting a femtosecond laser beam to process an internal portion of the object to be modified. The processing includes using a femtosecond laser beam to form a plurality of processing lines in the internal portion of the object to be modified, wherein each of the processing lines include a zigzag pattern processing, and a processing line spacing between the plurality of processing lines is in a range of 200 ?m to 600 ?m, wherein after the object to be modified is processed, a modified layer is formed in the object to be modified. Slicing or separating out a portion in the object to be modified that includes the modified layer.
    Type: Application
    Filed: August 23, 2023
    Publication date: March 7, 2024
    Applicants: GlobalWafers Co., Ltd., mRadian Femto Sources Co., Ltd.
    Inventors: Chien Chung Lee, Bo-Kai Wang, Shang-Chi Wang, Chia-Chi Tsai, I-Ching Li
  • Patent number: 11923422
    Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 5, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ming-Shien Hu, Chien-Jen Sun, I-Ching Li, Wen-Ching Hsu
  • Patent number: 11916018
    Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Yi Weng, Shih-Che Huang, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 11908753
    Abstract: Herein disclosed is a test head connection method, the method comprises the following steps. First, a load board and a card holder are provided between a test head and a probing machine, the card holder is disposed in the probing machine, and the card holder is used to accommodate the load board. A vacuum function of the test head is activated, and the test head is moved to align the card holder. The test head is moved to touch the load board in the card holder. At least one clamping piece is used to fix the test head and the card holder. Wherein the load board and a wafer are connected by direct probing.
    Type: Grant
    Filed: November 6, 2021
    Date of Patent: February 20, 2024
    Assignee: Chroma ATE Inc.
    Inventors: Kao-Shan Yang, Ching-Li Lin
  • Publication number: 20240033316
    Abstract: Provided is a nanoparticle or a pharmaceutical composition including the same for treating or remitting a neovascularization or an angiogenesis in eye segments, and the nanoparticle includes a hyaluronic acid and a therapeutic peptide.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Inventors: CHING-LI TSENG, YU-WEN CHENG, YU-YI WU, ERH-HSUAN HSIEH, JIA-HUA LIANG, FAN-LI LIN
  • Patent number: 11859965
    Abstract: A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: January 2, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Shang-Chi Wang, Wen-Ching Hsu, Chia-Chi Tsai, I-Ching Li
  • Patent number: 11852465
    Abstract: The disclosure provides a wafer inspection method and wafer inspection apparatus. The method includes: receive scanning information of at least one wafer, wherein the scanning information includes a plurality of haze values; the scanning information is divided into a plurality of information blocks according to the unit block, and the feature value of each of the plurality of information blocks is calculated according to the plurality of haze values included in each of the plurality of information blocks; and converting the feature value into a color value according to the haze upper threshold and the haze lower threshold, generating the color value corresponding to the at least one wafer according to the converted color value according to the feature value, whereby the color graph displays the texture content of the at least one wafer.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: December 26, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Shang-Chi Wang, Miao-Pei Chen, Han-Zong Wu, Chia-Chi Tsai, I-Ching Li
  • Patent number: 11845030
    Abstract: A dust collecting system for single crystal growth system includes an air compressor, a dust collecting device, a first inert gas source, a rotary pump and a scrubber. The air compressor is fluidly connected to an exit pipe of the single crystal growth system. The exit pipe is used to exhaust unstable dust from the single crystal growth system. The dust collecting device is fluidly connecting to the exit pipe to collect the dust oxide. The first inert gas source is fluidly connected to the exit pipe to blow a first inert gas into the exit pipe to compel the dust oxide toward the dust collecting device. The rotary pump is fluidly connected to the dust collecting device. The scrubber is fluidly connected to the rotary pump. The rotary pump transports the residual dust oxide toward the scrubber. The present disclosure further provides a method for collecting dust.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 19, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Masami Nakanishi, Yu-Sheng Su, I-Ching Li
  • Publication number: 20230347271
    Abstract: A method for collecting dust from a single crystal growth system includes providing dry air and oxygen into an exit pipe connecting to the single crystal growth system, blowing a first inert gas into the exit pipe to compel the dust oxide toward a dust collecting device, collecting the dust oxide by the dust collecting device; and providing a rotary pump to transport residues of the dust oxide backward. The oxygen reacts with the unstable dust for forming dust oxide. The exit pipe is used to exhaust unstable dust from the single crystal growth system.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 2, 2023
    Inventors: Masami Nakanishi, YU-SHENG SU, I-CHING LI
  • Publication number: 20230326882
    Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.
    Type: Application
    Filed: May 2, 2022
    Publication date: October 12, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lung Chou, Ching-Li Yang, Chih-Sheng Chang, Chien-Ting Lin
  • Patent number: 11762439
    Abstract: The present invention provides a method of dynamic thermal management applied to a portable device, wherein the method includes the steps of: obtaining a surface temperature of the portable device; obtaining a junction temperature of a chip of the portable device; and calculating an upper limit of the junction temperature according to the junction temperature and the surface temperature.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 19, 2023
    Assignee: MEDIATEK INC.
    Inventors: Pei-Yu Huang, Chih-Yuan Hsiao, Chiao-Pin Fan, Chi-Wen Pan, Tai-Yu Chen, Chien-Tse Fang, Jih-Ming Hsu, Yun-Ching Li