Patents by Inventor Ching-Liang Huang

Ching-Liang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972984
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: April 30, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20240124350
    Abstract: A quantum dot composite structure and a method for forming the same are provided. The quantum dot composite structure includes: a glass particle including a glass matrix and a plurality of quantum dots located in the glass matrix, wherein at least one of the plurality of quantum dots includes an exposed surface in the glass matrix; and an inorganic protective layer disposed on the glass particle and covering the exposed surface.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 18, 2024
    Inventors: Ching LIU, Wen-Tse HUANG, Ru-Shi LIU, Pei Cong YAN, Chai-Chun HSIEH, Hung-Chun TONG, Yu-Chun LEE, Tzong-Liang TSAI
  • Patent number: 11545605
    Abstract: A display panel including a pixel circuit substrate, a planarization layer, a plurality of bonding pads, a plurality of light-emitting devices, a plurality of auxiliary electrodes, and a reflective structure layer is provided. The pixel circuit substrate has a plurality of signal lines. The planarization layer covers the signal lines. The bonding pads are disposed on the planarization layer and are electrically connected to the signal lines. The light-emitting devices are electrically bonded to the bonding pads. The auxiliary electrodes are disposed between the bonding pads. The reflective structure layer is disposed between the light-emitting devices and overlaps at least part of the auxiliary electrodes and the bonding pads. A method of fabricating the display panel is also provided.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: January 3, 2023
    Assignee: Au Optronics Corporation
    Inventors: Hsun-Yi Wang, Chan-Jui Liu, Chiao-Li Huang, Ching-Liang Huang, Chun-Cheng Cheng
  • Publication number: 20220376150
    Abstract: A display panel including a pixel circuit substrate, a planarization layer, a plurality of bonding pads, a plurality of light-emitting devices, a plurality of auxiliary electrodes, and a reflective structure layer is provided. The pixel circuit substrate has a plurality of signal lines. The planarization layer covers the signal lines. The bonding pads are disposed on the planarization layer and are electrically connected to the signal lines. The light-emitting devices are electrically bonded to the bonding pads. The auxiliary electrodes are disposed between the bonding pads. The reflective structure layer is disposed between the light-emitting devices and overlaps at least part of the auxiliary electrodes and the bonding pads. A method of fabricating the display panel is also provided.
    Type: Application
    Filed: November 4, 2021
    Publication date: November 24, 2022
    Applicant: Au Optronics Corporation
    Inventors: Hsun-Yi Wang, Chan-Jui Liu, Chiao-Li Huang, Ching-Liang Huang, Chun-Cheng Cheng
  • Publication number: 20210343526
    Abstract: A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Applicant: Au Optronics Corporation
    Inventors: Jia-Hong Ye, Ching-Liang Huang
  • Patent number: 11094540
    Abstract: A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 17, 2021
    Assignee: Au Optronics Corporation
    Inventors: Jia-Hong Ye, Ching-Liang Huang
  • Patent number: 10566357
    Abstract: The present invention provides a method for crystallizing a metal oxide semiconductor layer, a semiconductor structure, a method for manufacturing a semiconductor structure, an active array substrate, and an indium gallium zinc oxide crystal. The crystallization method includes the following steps: forming an amorphous metal oxide semiconductor layer on a substrate; forming an oxide layer on the amorphous metal oxide semiconductor layer; forming an amorphous silicon layer on the oxide layer; and irradiating the amorphous silicon layer by using a laser, so as to heat the amorphous silicon layer, where the heated amorphous silicon layer heats the amorphous metal oxide semiconductor layer, so that the amorphous metal oxide semiconductor layer is converted into a crystallized metal oxide semiconductor layer.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 18, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Jia-Hong Ye, Ching-Liang Huang
  • Publication number: 20190304779
    Abstract: A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Applicant: Au Optronics Corporation
    Inventors: Jia-Hong Ye, Ching-Liang Huang
  • Patent number: 10382228
    Abstract: In the subject system, a customer virtual local network (VLAN) tag is protected using, for example, media access control security (MACSec). MACSec authentication is performed on a packet by including the VLAN tag in an integrity check value (ICV) computation. When a packet is received from an Ethernet Virtual Connection (EVC) at an ingress port of the subject system, a remote site is identified and an associated VLAN tag is determined based on the identified remote site and a VLAN tag associated with the packet. The subject system may perform VLAN tag mapping to account for changes in a VLAN tag across EVCs. An ICV is computed based on the determined VLAN tag and compared with an ICV stored in the received packet. The integrity check passes when the computed ICV matches the stored ICV and fails when the computed ICV does not match the stored ICV.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: August 13, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventor: Ching-Liang Huang
  • Publication number: 20180166474
    Abstract: The present invention provides a method for crystallizing a metal oxide semiconductor layer, a semiconductor structure, a method for manufacturing a semiconductor structure, an active array substrate, and an indium gallium zinc oxide crystal. The crystallization method includes the following steps: forming an amorphous metal oxide semiconductor layer on a substrate; forming an oxide layer on the amorphous metal oxide semiconductor layer; forming an amorphous silicon layer on the oxide layer; and irradiating the amorphous silicon layer by using a laser, so as to heat the amorphous silicon layer, where the heated amorphous silicon layer heats the amorphous metal oxide semiconductor layer, so that the amorphous metal oxide semiconductor layer is converted into a crystallized metal oxide semiconductor layer.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 14, 2018
    Inventors: Jia-Hong YE, Ching-Liang HUANG
  • Publication number: 20150381531
    Abstract: In the subject system, a customer virtual local network (VLAN) tag is protected using, for example, media access control security (MACSec). MACSec authentication is performed on a packet by including the VLAN tag in an integrity check value (ICV) computation. When a packet is received from an Ethernet Virtual Connection (EVC) at an ingress port of the subject system, a remote site is identified and an associated VLAN tag is determined based on the identified remote site and a VLAN tag associated with the packet. The subject system may perform VLAN tag mapping to account for changes in a VLAN tag across EVCs. An ICV is computed based on the determined VLAN tag and compared with an ICV stored in the received packet. The integrity check passes when the computed ICV matches the stored ICV and fails when the computed ICV does not match the stored ICV.
    Type: Application
    Filed: June 2, 2015
    Publication date: December 31, 2015
    Inventor: Ching-Liang HUANG
  • Patent number: 7120683
    Abstract: An architecture for creating a single image for a stack of switches. A plurality of the internetworking devices are provided in a stack configuration for interconnecting networks. Software is executed in each internetworking device such that the stack of internetworking devices appear as a single internetworking device to the interconnected networks.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: October 10, 2006
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventor: James Ching-Liang Huang
  • Publication number: 20020046271
    Abstract: An architecture for creating a single image for a stack of switches. A plurality of the internetworking devices are provided in a stack configuration for interconnecting networks. Software is executed in each internetworking device such that the stack of internetworking devices appear as a single internetworking device to the interconnected networks.
    Type: Application
    Filed: April 3, 2001
    Publication date: April 18, 2002
    Inventor: James Ching-Liang Huang
  • Patent number: D426707
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: June 20, 2000
    Inventors: Ching-Liang Huang, Ling-Fang Lee