Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A defect detection and removal apparatus including a removing unit, an image capturing unit, and a determining unit is provided. The removing unit is configured to remove at least one defective micro-element on a substrate. The image capturing unit is configured to capture a detection image of at least one defective micro-element correspondingly on the substrate. The determining unit is coupled to the image capturing unit and the removing unit. The image capturing unit executes capturing a first detection image before the removing unit executes removing a defective micro-element, and executes capturing a second detection image after the removing unit executes removing the defective micro-element. The determining unit confirms whether the defective micro-element has been removed according to the first and second detection image obtained from the image capturing unit. A defect detection and removal method is also provided.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Abstract: A micro LED display panel includes a driving substrate and a plurality of micro light emitting diodes (LEDs). The driving substrate has a plurality of pixel regions. Each of the pixel regions includes a plurality of sub-pixel regions. The micro LEDs are located on the driving substrate. At least one of the sub-pixel regions is provided with two micro LEDs of the micro LEDs electrically connected in series, and a dominant wavelength of the two micro LEDs is within a wavelength range of a specific color light. In a repaired sub-pixel region of the sub-pixel regions, only one of the two micro LEDs emits light. In a normal sub-pixel region of the sub-pixel regions, both of the two micro LEDs emit light.

Abstract: A micro LED display panel includes a driving substrate and a plurality of micro light emitting diodes (LEDs). The driving substrate has a plurality of pixel regions. Each of the pixel regions includes a plurality of sub-pixel regions. The micro LEDs are located on the driving substrate. At least one of the sub-pixel regions is provided with two micro LEDs of the micro LEDs electrically connected in series, and a dominant wavelength of the two micro LEDs is within a wavelength range of a specific color light. In a repaired sub-pixel region of the sub-pixel regions, only one of the two micro LEDs emits light. In a normal sub-pixel region of the sub-pixel regions, both of the two micro LEDs emit light.

Abstract: A display panel and a repairing method thereof. The display panel includes micro LEDs and a circuit substrate. The circuit substrate includes first wires, second wires and connecting circuits. Respective one of the connecting circuits is configured to be electrically connected to respective one of the micro LEDs. Each of the connecting circuits includes a first pad, a second pad, a third pad and a connecting wire. The first pad is configured to be electrically connected to the corresponding micro LED and one of the first wires. The first and second pads are separated by a first gap. The second pad is configured to be electrically connected to one of the second wires. The second and third pads are separated by a second gap. The connecting wire is connected to the second pad and the third pad.

Abstract: A display panel and a repairing method thereof. The display panel includes micro LEDs and a circuit substrate. The circuit substrate includes first wires, second wires and connecting circuits. Respective one of the connecting circuits is configured to be electrically connected to respective one of the micro LEDs. Each of the connecting circuits includes a first pad, a second pad, a third pad and a connecting wire. The first pad is configured to be electrically connected to the corresponding micro LED and one of the first wires. The first and second pads are separated by a first gap. The second pad is configured to be electrically connected to one of the second wires. The second and third pads are separated by a second gap. The connecting wire is connected to the second pad and the third pad.

Abstract: A display panel includes a driving substrate and a plurality of micro light emitting diodes (LEDs). The driving substrate has a plurality of pixel regions. The micro LEDs are located on the driving substrate and arranged apart from each other. The micro LEDs at least includes a plurality of first micro LEDs and a plurality of second micro LEDs. Each of the pixel regions is at least provided with one first micro LED and one second micro LED, and the first micro LED and the second micro LED are electrically connected in series.

Abstract: A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising AlxInyGa1-x-yN layers, at least one GaN based layer, and an ohmic contact layer. The light emitting layer is disposed on the first-type doped semiconductor layer, and the second-type doped semiconductor layer is disposed on the light emitting layer. The AlxInyGa1-x-yN layers stacked on the light emitting layer, where 0<x<1, 0?y<1, and 0<x+y<1, and the GaN based layer interposed between two of the AlxInyGa1-x-yN layers, and the ohmic contact layer is disposed on the AlxInyGa1-x-yN layers.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1-xN (0<x<1) while the stress control layer is made from AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.

Abstract: A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising AlxInyGal-x-yN layers, at least one GaN based layer, and an ohmic contact layer. The light emitting layer is disposed on the first-type doped semiconductor layer, and the second-type doped semiconductor layer is disposed on the light emitting layer. The AlxInyGal-x-yN layers stacked on the light emitting layer, where 0<x<1, 0?y<1, and 0<x+y<1, and the GaN based layer interposed between two of the AlxInyGal-x-yN layers, and the ohmic contact layer is disposed on the AlxInyGal-x-yN layers.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1-xN (0<x<1) while the stress control layer is made from AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.

Abstract: A semiconductor light emitting device including an N-type semiconductor layer, a P-type semiconductor layer, a light emitting layer and a strain relief layer is provided. The light emitting layer is disposed between the N-type semiconductor layer and the P-type semiconductor layer, and the light emitting layer is a multiple quantum well structure. The strain relief layer is disposed between the light emitting layer and the N-type semiconductor layer, and is made of InxGa1-xN, where 0<x<1. The difference between any two values of x corresponded to any two positions in the strain relief layer is greater than ?0.01 and less than 0.01. The thickness of the strain relief layer is larger than the thickness of each well layer of the multiple quantum well structure.

Abstract: A semiconductor light-emitting device including at least one n-type semiconductor layer, at least one p-type semiconductor layer, and a light-emitting layer is provided. The light-emitting layer is disposed between the at least one p-type semiconductor layer and the at least one n-type semiconductor layer. A ratio of carbon concentration to aluminum concentration in any one semiconductor layer containing aluminum in the semiconductor light-emitting device ranges from 10?4 to 10?2.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1-xN (0<x<1) while the stress control layer is made from AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.

Abstract: A semiconductor light emitting device including an N-type semiconductor layer, a P-type semiconductor layer, a light emitting layer and a strain relief layer is provided. The light emitting layer is disposed between the N-type semiconductor layer and the P-type semiconductor layer, and the light emitting layer is a multiple quantum well structure. The strain relief layer is disposed between the light emitting layer and the N-type semiconductor layer, and is made of InxGa1-xN, where 0<x<1. The difference between x's at any two positions in the strain relief layer is greater than ?0.01 and less than 0.01. The thickness of the strain relief layer is larger than the thickness of each well layer of the multiple quantum well structure.

Abstract: A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a temporary substrate and light-emitting elements; disconnecting the light-emitting elements from the temporary substrate to allow the light-emitting elements to float on a fluid; adjusting spacings between the light-emitting elements to have a predetermined size by controlling flow of the fluid; placing a package substrate into the fluid, followed by aligning the light-emitting elements with connecting pads of the package substrate so as to correspondingly place the light-emitting elements on the connecting pads; and removing the package substrate with the light-emitting elements from the fluid.

Abstract: A semiconductor light-emitting device including a first N-type semiconductor layer, a P-type semiconductor layer, and a light-emitting layer is provided. The first N-type semiconductor layer contains aluminum, and the concentration of the N-type dopant thereof is greater than or equal to 5×1018 atoms/cm3. The light-emitting layer is disposed between the first N-type semiconductor layer and the P-type semiconductor layer. A manufacturing method of a semiconductor light-emitting device is also provided.

Abstract: A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a temporary substrate and light-emitting elements; disconnecting the light-emitting elements from the temporary substrate to allow the light-emitting elements to float on a fluid; adjusting spacings between the light-emitting elements to have a predetermined size by controlling flow of the fluid; placing a package substrate into the fluid, followed by aligning the light-emitting elements with connecting pads of the package substrate so as to correspondingly place the light-emitting elements on the connecting pads; and removing the package substrate with the light-emitting elements from the fluid.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1-xN (0<x<1) while the stress control layer is made from AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.