Patents by Inventor Ching-Lin Jiang
Ching-Lin Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6118690Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.Type: GrantFiled: November 27, 1995Date of Patent: September 12, 2000Assignee: Dallas Semiconductor CorporationInventors: Ching-Lin Jiang, Clark R. Williams
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Patent number: 5532958Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.Type: GrantFiled: November 24, 1993Date of Patent: July 2, 1996Assignee: Dallas Semiconductor Corp.Inventors: Ching-Lin Jiang, Clark R. Williams
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Patent number: 5351208Abstract: A content addressable memory is provided that includes a memory cell and a first plurality of lines connected directly to the gates of access transistors to this memory cell. These access transistors are further connected to a second plurality of lines. The first and second plurality of lines each perform different functions during read, write, and comparison modes. In another embodiment of the present invention, p-channel transistors are used for a match transistor and its associated pass transistors.Type: GrantFiled: April 27, 1992Date of Patent: September 27, 1994Assignee: Integrated Information Technology, Inc.Inventor: Ching-Lin Jiang
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Patent number: 5339076Abstract: A data compression/decompression processor implements a modified Ziv-Lempel ("LZ") coding technique. The processor includes three modules, an interface, a coder-decoder ("CODEC"), and a MODEL. The CODEC and the MODEL modules together form compression engine, in which the CODEC provides variable length coding and data packing, and the MODEL implements the LZ processing. The MODEL uses content addressable memory ("CAM") in encoding mode for text storage and character matching, and uses CAM in decoding mode as an on-chip RAM to obtain high speed access.Type: GrantFiled: April 27, 1992Date of Patent: August 16, 1994Assignee: Integrated Information TechnologyInventor: Ching-Lin Jiang
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Patent number: 5299156Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.Type: GrantFiled: June 25, 1990Date of Patent: March 29, 1994Assignee: Dallas Semiconductor Corp.Inventors: Ching-Lin Jiang, Clark R. Williams
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Patent number: 5162757Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during startup.Type: GrantFiled: March 27, 1990Date of Patent: November 10, 1992Inventors: Clark R. Williams, Ching-Lin Jiang
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Patent number: 5150079Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.Type: GrantFiled: June 18, 1991Date of Patent: September 22, 1992Assignee: Dallas Semiconductor CorporationInventors: Clark R. Williams, Ching-Lin Jiang
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Patent number: 4940910Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.Type: GrantFiled: June 2, 1989Date of Patent: July 10, 1990Assignee: Dallas Semiconductor CorporationInventor: Ching-Lin Jiang
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Patent number: 4912435Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.Type: GrantFiled: September 7, 1989Date of Patent: March 27, 1990Assignee: Dallas Semiconductor CorporationInventors: Clark R. Williams, Ching-Lin Jiang
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Patent number: 4894791Abstract: A delay circuit that can be implemented in a monolithic integrated circuit includes a plurality of capacitor/laser-fusible link series pairs. Delay of a binary output signal of the circuit with respect to an input transition is directly proportional to the amount of capacitance connected into the circuit. Because the laser-fusible links can selectively be opened with a laser, the amount of capacitance connected into the circuit can incrementally be reduced; thus, the delay of the circuit is reducibly adjustable to a desired value. By including a plurality of conductive element/laser-fusible link series pairs in the delay circuit, the delay of the circuit is also increasingly adjustable.Type: GrantFiled: February 10, 1986Date of Patent: January 16, 1990Assignee: Dallas Semiconductor CorporationInventors: Ching-Lin Jiang, William J. Podkowa
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Patent number: 4873665Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.Type: GrantFiled: June 7, 1988Date of Patent: October 10, 1989Assignee: Dallas Semiconductor CorporationInventors: Ching-Lin Jiang, Clark R. Williams
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Patent number: 4871982Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.Type: GrantFiled: October 28, 1988Date of Patent: October 3, 1989Assignee: Dallas Semiconductor CorporationInventors: Clark R. Williams, Ching-Lin Jiang
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Patent number: 4843265Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.Type: GrantFiled: June 30, 1988Date of Patent: June 27, 1989Assignee: Dallas Semiconductor CorporationInventor: Ching-Lin Jiang
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Patent number: 4730346Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.Type: GrantFiled: February 12, 1987Date of Patent: March 8, 1988Assignee: Dallas Semiconductor CorporationInventor: Ching-Lin Jiang
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Patent number: 4654829Abstract: A portable, non-volatile read/write memory module includes a battery for providing standby power that is coupled to a monolithic integrated circuit. Five terminals of the module are removably connected to a host electronic system for transfer of data to and from the module. One of the terminals is a chip enable input that may optionally be used for providing operating power to the monolithic integrated circuit. The monolithic integrated circuit further includes control circuitry that may optionally be coded for providing a security feature for access to data stored in the memory module.Type: GrantFiled: December 17, 1984Date of Patent: March 31, 1987Assignee: Dallas Semiconductor CorporationInventors: Ching-Lin Jiang, Robert D. Lee
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Patent number: 4645943Abstract: A space-saving back-up power supply apparatus has length and width dimensions substantially the same as those of a conventional integrated circuit connector. The apparatus includes sockets arranged on its top for making connection to a socket-pluggable integrated circuit such as a standard CMOS RAM, and the apparatus has pins extending from its bottom for making connection to a printed circuit board or connector of a host electronic system. Control circuitry and one or more batteries are located within the apparatus. The back-up power supply is operative to provide power to the socket-pluggable integrated circuit even if the normal power supply of the host electronic system is short-circuited. The control circuitry of the back-up power supply controls the chip enable signal and performs a battery test upon power-up.Type: GrantFiled: October 15, 1984Date of Patent: February 24, 1987Assignee: Dallas Semiconductor CorporationInventors: John W. Smith, Jr., Francis A. Scherpenberg, Ching-Lin Jiang, Michael L. Bolan
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Patent number: 4613959Abstract: A redundancy circuit that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated by blowing a pair of fuses.Type: GrantFiled: January 6, 1984Date of Patent: September 23, 1986Assignee: Thomson Components-Mostek CorportionInventor: Ching-Lin Jiang
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Patent number: 4545035Abstract: A compact memory cell combines a volatile dynamic storage section with a shadow nonvolatile section in two vertically stacked element arrays.Type: GrantFiled: July 20, 1982Date of Patent: October 1, 1985Assignee: Mostek CorporationInventors: Daniel C. Guterman, Ching-Lin Jiang
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Patent number: 4535427Abstract: A FIFO memory chip includes read and write pointers in the form of an X and a Y shift register carrying a pair of pointer bits that point to a memory cell in a rectangular cell array.Type: GrantFiled: December 6, 1982Date of Patent: August 13, 1985Assignee: Mostek CorporationInventor: Ching-Lin Jiang
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Patent number: RE34241Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of the bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.Type: GrantFiled: March 8, 1990Date of Patent: May 4, 1993Assignee: Dallas Semiconductor Corp.Inventor: Ching-Lin Jiang