Patents by Inventor Ching-Ling Lin

Ching-Ling Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021772
    Abstract: An optoelectronic semiconductor device is provided. The optoelectronic semiconductor device includes an epitaxial stack, a trench, a concave portion, a first contact structure, and a first electrode. The epitaxial stack includes a first semiconductor structure, an active structure on the first semiconductor structure, and a second semiconductor structure on the active structure, wherein the epitaxial stack has a first portion and a second portion, and the second semiconductor structure of the first portion is separated from the second semiconductor structure of the second portion. The trench is located between the first portion and the second portion. The concave portion is located in the first portion. The first contact structure is located in the concave portion. The first electrode covers the first contact structure. When the optoelectronic semiconductor device is operating, the first portion does not emit light.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 18, 2024
    Inventors: Ching-En Huang, Hao-Ming Ku, Shih-I Chen, Tzu-Ling Yang, Ya-Wen Lin, Chuang-Sheng Lin, Yi-Chia Ho
  • Patent number: 11855199
    Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ling Yeh, Pravanshu Mohanta, Ching-Yu Chen, Jiang-He Xie, Yu-Shine Lin
  • Publication number: 20230377883
    Abstract: A system and method utilize directed self-assembly films, including block copolymers and solvents, to form features on a wafer. The solvents have high boiling points. The high boiling points of the solvents enable directed self-assembly processes to utilize very high temperature, rapid thermal annealing processes to generate a pattern of first and second polymer structures over a wafer from the directed self-assembly films. The pattern of the first and second polymer structures can be utilized to form the features on the wafer.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Yu-Ling CHANG CHIEN, Yu-Chung SU, Yahru CHENG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Patent number: 11759812
    Abstract: An apparatus for manufacturing golf balls each having an exterior pattern includes a conveying device and a spraying device. The spraying device is disposed at one side of a first processing area. The conveying device is configured to convey a ball-shaped body into the first processing area along a predetermined path, and to rotate the ball-shaped body at a predetermined speed. The spraying device includes a first sprayer and a second sprayer. The first sprayer and the second sprayer are configured to apply a color paint to the ball-shaped body from each of an upper position and a lower position.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 19, 2023
    Assignee: FOREMOST GOLF MFG. LTD.
    Inventors: Chia-Sheng Huang, Chi-Ling Lin, Chia-Cheng Wu, Ching-Hsiang Liu
  • Publication number: 20230201266
    Abstract: The present disclosure provides a method for treating arthritis by using a stem cell preparation. The stem cell preparation of the present disclosure can effectively delay cartilage degeneration caused by arthritis, and it is confirmed by whole blood analysis and blood biochemical analysis that the stem cell preparation in the form of three-dimensional stem cell spheres provides a safe treatment for arthritis. The present disclosure also provides a method for preparing the stem cell preparation.
    Type: Application
    Filed: September 9, 2021
    Publication date: June 29, 2023
    Inventors: Feng-Huei Lin, Che-Yung Kuan, Yu-Ying Lin, Ching-Yun Chen, Zhi-Yu Chen, I-Hsuan Yang, Ming-Hsi Chuang, Po-Cheng Lin, Chia-Hsin Lee, Kai-Ling Zhang, Pei-Syuan Chao, Wan-Sin Syu, Chun-Hung Chen, Ting-Ju Wang
  • Publication number: 20230135742
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Application
    Filed: December 26, 2022
    Publication date: May 4, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 11569133
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: January 31, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10892194
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200328126
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200258788
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10741455
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10679903
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 9, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20200176331
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10607897
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200035568
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 30, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10475709
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to forma first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20190172753
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.
    Type: Application
    Filed: January 2, 2018
    Publication date: June 6, 2019
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10312146
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 4, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10204981
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: February 12, 2019
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Ching-Ling Lin
  • Publication number: 20190019731
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: July 11, 2017
    Publication date: January 17, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang