Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, wherein the plurality of gate structures comprises at least one first gate structure and at least one second gate structure, at least one first metal layer located on the first gate structure, wherein the first metal layer is electrically connected with the first gate structure, and at least one second metal layer bridging the second gate structure and another one of the plurality of gate structures, wherein a top surface of the first gate structure is lower than a top surface of the second gate structure.

Abstract: The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

Abstract: The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

Abstract: A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a core region and an input/output (I/O) region and then forming a first metal gate on the core region and a second metal gate on the I/O region. Preferably, the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer having different shapes such that the first gate dielectric layer includes an I-shape and the second gate dielectric layer includes a U-shape.

Abstract: A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure, performing a first etching process to remove the ILD layer, performing a second etching process to remove the CESL for forming a first contact hole, and then forming a first contact plug in the first contact hole. Preferably, a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

Abstract: The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.