Patents by Inventor Ching-Ling Lin
Ching-Ling Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973425Abstract: A power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit generates an output signal according to an input signal and a control signal. The ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. The control circuit generates the control signal according to the output signal, a reference signal, and the ramp signal.Type: GrantFiled: December 29, 2021Date of Patent: April 30, 2024Assignee: NOVATEK Microelectronics Corp.Inventors: Chieh-Ju Tsai, Ching-Jan Chen, Zhen-Guo Ding, Zhe-Hui Lin, Wei-Ling Chen
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Patent number: 11972984Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: GrantFiled: December 26, 2022Date of Patent: April 30, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Publication number: 20240136291Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.Type: ApplicationFiled: January 12, 2023Publication date: April 25, 2024Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
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Patent number: 11965069Abstract: A heat-shrinkable polyester film made of a polyester-forming resin composition includes a recycled material, and has an exothermic crystallization peak and an endothermic melting peak which are determined via differential scanning calorimetry, and which satisfy relationships of T2?T1?68° C. and T3?T2?78° C., where T1 represents an onset point of the exothermic crystallization peak, T2 represents an end point of the exothermic crystallization peak and an onset point of the endothermic melting peak, and T3 represents an end point of the endothermic melting peak. A method for manufacturing the heat-shrinkable polyester film is also disclosed.Type: GrantFiled: February 5, 2021Date of Patent: April 23, 2024Assignee: FAR EASTERN NEW CENTURY CORPORATIONInventors: Li-Ling Chang, Yow-An Leu, Ting-Yu Lin, Ching-Chun Tsai, Wen-Yi Chang
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Patent number: 11964299Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.Type: GrantFiled: October 26, 2021Date of Patent: April 23, 2024Assignee: FOREMOST GOLF MFG. LTD.Inventors: Chia-Sheng Huang, Chi-Ling Lin, Chia-Cheng Wu, Ching-Hsiang Liu
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240088284Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Chia-Ling YEH, Pravanshu MOHANTA, Ching-Yu CHEN, Jiang-He XIE, Yu-Shine LIN
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Publication number: 20230135742Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: ApplicationFiled: December 26, 2022Publication date: May 4, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Patent number: 11569133Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: GrantFiled: April 27, 2020Date of Patent: January 31, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Patent number: 10892194Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.Type: GrantFiled: June 29, 2020Date of Patent: January 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
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Publication number: 20200328126Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
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Publication number: 20200258788Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Patent number: 10741455Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.Type: GrantFiled: February 5, 2020Date of Patent: August 11, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
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Patent number: 10679903Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.Type: GrantFiled: January 2, 2018Date of Patent: June 9, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Publication number: 20200176331Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.Type: ApplicationFiled: February 5, 2020Publication date: June 4, 2020Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
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Patent number: 10607897Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.Type: GrantFiled: September 30, 2019Date of Patent: March 31, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
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Publication number: 20200035568Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.Type: ApplicationFiled: September 30, 2019Publication date: January 30, 2020Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
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Patent number: 10475709Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to forma first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.Type: GrantFiled: July 10, 2018Date of Patent: November 12, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
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Publication number: 20190172753Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.Type: ApplicationFiled: January 2, 2018Publication date: June 6, 2019Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Patent number: 10312146Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.Type: GrantFiled: July 11, 2017Date of Patent: June 4, 2019Assignee: United Microelectronics Corp.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang