Patents by Inventor Ching-Ling Tsai
Ching-Ling Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973425Abstract: A power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit generates an output signal according to an input signal and a control signal. The ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. The control circuit generates the control signal according to the output signal, a reference signal, and the ramp signal.Type: GrantFiled: December 29, 2021Date of Patent: April 30, 2024Assignee: NOVATEK Microelectronics Corp.Inventors: Chieh-Ju Tsai, Ching-Jan Chen, Zhen-Guo Ding, Zhe-Hui Lin, Wei-Ling Chen
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Patent number: 11965069Abstract: A heat-shrinkable polyester film made of a polyester-forming resin composition includes a recycled material, and has an exothermic crystallization peak and an endothermic melting peak which are determined via differential scanning calorimetry, and which satisfy relationships of T2?T1?68° C. and T3?T2?78° C., where T1 represents an onset point of the exothermic crystallization peak, T2 represents an end point of the exothermic crystallization peak and an onset point of the endothermic melting peak, and T3 represents an end point of the endothermic melting peak. A method for manufacturing the heat-shrinkable polyester film is also disclosed.Type: GrantFiled: February 5, 2021Date of Patent: April 23, 2024Assignee: FAR EASTERN NEW CENTURY CORPORATIONInventors: Li-Ling Chang, Yow-An Leu, Ting-Yu Lin, Ching-Chun Tsai, Wen-Yi Chang
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 10622347Abstract: An electrostatic discharge protection (ESD) structure for protecting a core circuit of an integrated circuit from an ESD event received by a conductive pad of the integrated circuit is provided. The ESD protection structure includes a first conductive layer, a clamp device, a first electrical connection part and a second electrical connection part. The first conductive layer is formed below the conductive pad, and includes a first conductive portion, an insulating portion and a second conductive portion. The insulating portion is surrounded by the first conductive portion and the second conductive portion. The first conductive portion is electrically connected between the conductive pad and the second conductive portion. The clamp device is arranged for clamping the ESD event. The first electrical connection part is coupled between the first conductive portion and the clamp device. The second electrical connection part is coupled between the second conductive portion and the core circuit.Type: GrantFiled: July 6, 2017Date of Patent: April 14, 2020Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Hung-Yi Chen, Ching-Ling Tsai
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Publication number: 20190013309Abstract: An electrostatic discharge protection (ESD) structure for protecting a core circuit of an integrated circuit from an ESD event received by a conductive pad of the integrated circuit is provided. The ESD protection structure includes a first conductive layer, a clamp device, a first electrical connection part and a second electrical connection part. The first conductive layer is formed below the conductive pad, and includes a first conductive portion, an insulating portion and a second conductive portion. The insulating portion is surrounded by the first conductive portion and the second conductive portion. The first conductive portion is electrically connected between the conductive pad and the second conductive portion. The clamp device is arranged for clamping the ESD event. The first electrical connection part is coupled between the first conductive portion and the clamp device. The second electrical connection part is coupled between the second conductive portion and the core circuit.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Hung-Yi Chen, Ching-Ling Tsai
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Patent number: 9001478Abstract: A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.Type: GrantFiled: December 16, 2011Date of Patent: April 7, 2015Assignees: National Chiao-Tung University, Himax Technologies LimitedInventors: Ming-Dou Ker, Cheng-Cheng Yen, Tung-Yang Chen, Ching-Ling Tsai, Shih-Fan Chen
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Publication number: 20130155566Abstract: A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicants: HIMAX TECHNOLOGIES LIMITED, NATIONAL CHIAO-TUNG UNIVERSITYInventors: MING-DOU KER, Cheng-Cheng Yen, Tung-Yang CHEN, Ching-Ling Tsai, Shih-Fan Chen
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Patent number: 8397201Abstract: A method of simulating an electrostatic discharge (ESD) circuit layout is disclosed. A netlist of an electronic circuit is pre-simulated. A circuit layout, including an ESD circuit layout, is accordingly generated. Parasitic is extracted according to the generated circuit layout. The ESD circuit layout is post-simulated according to an ESD waveform and a result of the parasitic extraction.Type: GrantFiled: August 11, 2011Date of Patent: March 12, 2013Assignee: Himax Technologies LimitedInventors: Ching-Ling Tsai, Shih-Fan Chen
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Publication number: 20130050884Abstract: An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region, a first isolation structure and a first N type doped region. The first isolation structure is disposed inside the first P type doped region, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and drains it away, and the parasitical capacitance of the P type ESD protection element decreases based on the area of the first P type doped region.Type: ApplicationFiled: August 23, 2011Publication date: February 28, 2013Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Ching-Ling Tsai, Sheng-Fan Yang, Shih-Fan Chen
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Publication number: 20130043555Abstract: An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region and a first N type doped region. The covered shape of the first P type doped region is a polygon having at least eight edges, wherein the polygon is bilateral symmetry, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and uniformly drains it away.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Ching-Ling Tsai
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Publication number: 20130044396Abstract: An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region and a first N type doped region. The covered shape of the first P type doped region is circular, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and uniformly drains it away.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Ching-Ling Tsai, Shih-Fan Chen, Yu-Wei Huang
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Publication number: 20130042218Abstract: A method of simulating an electrostatic discharge (ESD) circuit layout is disclosed. A netlist of an electronic circuit is pre-simulated. A circuit layout, including an ESD circuit layout, is accordingly generated. Parasitic is extracted according to the generated circuit layout. The ESD circuit layout is post-simulated according to an ESD waveform and a result of the parasitic extraction.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Ching-Ling Tsai, Shih-Fan Chen
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Patent number: 8196078Abstract: A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.Type: GrantFiled: February 11, 2010Date of Patent: June 5, 2012Assignee: Himax Technologies LimitedInventors: Tung-Yang Chen, Ching-Ling Tsai, Sheng-Fan Yang, Jui-Ni Lee
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Publication number: 20100235798Abstract: A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.Type: ApplicationFiled: February 11, 2010Publication date: September 16, 2010Inventors: Tung-Yang Chen, Ching-Ling Tsai, Sheng-Fan Yang, Jui-Ni Lee