Patents by Inventor Ching-Liou Huang
Ching-Liou Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230118028Abstract: Integrated circuit (IC) packages employing a supplemental metal layer with coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer to reduce metal density mismatch, and related fabrication methods. An IC package includes a semiconductor die (“die”) electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer adjacent to and coupled to the die. To reduce or avoid metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate, a supplemental metal layer with additional metal interconnects is disposed adjacent to the die-size ETS metallization layer. The additional metal interconnects are coupled in a vertical direction to the embedded metal traces in the die-side ETS metallization layer to increase metal density of die-side metal interconnects formed by the additional metal interconnects coupled to the embedded metal traces in the die-side ETS metallization layer.Type: ApplicationFiled: October 18, 2021Publication date: April 20, 2023Inventors: Michelle Yejin Kim, Kuiwon Kang, Joan Rey Villarba Buot, Ching-Liou Huang
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Patent number: 11437307Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.Type: GrantFiled: November 11, 2020Date of Patent: September 6, 2022Assignee: QUALCOMM IncorporatedInventors: Abdolreza Langari, Yuan Li, Shrestha Ganguly, Terence Cheung, Ching-Liou Huang, Hui Wang
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Publication number: 20210066177Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.Type: ApplicationFiled: November 11, 2020Publication date: March 4, 2021Inventors: Abdolreza LANGARI, Yuan LI, Shrestha GANGULY, Terence CHEUNG, Ching-Liou HUANG, Hui WANG
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Patent number: 10916494Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.Type: GrantFiled: June 26, 2019Date of Patent: February 9, 2021Assignee: QUALCOMM IncorporatedInventors: Abdolreza Langari, Yuan Li, Shrestha Ganguly, Terence Cheung, Ching-Liou Huang, Hui Wang
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Publication number: 20200211943Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.Type: ApplicationFiled: June 26, 2019Publication date: July 2, 2020Inventors: Abdolreza LANGARI, Yuan LI, Shrestha GANGULY, Terence CHEUNG, Ching-Liou HUANG, Hui WANG
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Patent number: 10312210Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.Type: GrantFiled: April 10, 2018Date of Patent: June 4, 2019Assignee: MediaTek Inc.Inventors: Ching-Liou Huang, Ta-Jen Yu
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Publication number: 20180233476Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.Type: ApplicationFiled: April 10, 2018Publication date: August 16, 2018Applicant: MediaTek Inc.Inventors: Ching-Liou Huang, Ta-Jen Yu
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Patent number: 9972593Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.Type: GrantFiled: November 7, 2014Date of Patent: May 15, 2018Assignee: MediaTek Inc.Inventors: Ching-Liou Huang, Ta-Jen Yu
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Patent number: 9659893Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.Type: GrantFiled: August 14, 2015Date of Patent: May 23, 2017Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
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Patent number: 9640505Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.Type: GrantFiled: August 13, 2015Date of Patent: May 2, 2017Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
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Patent number: 9548271Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer.Type: GrantFiled: November 4, 2015Date of Patent: January 17, 2017Assignee: MEDIATEK INC.Inventors: Kuei-Ti Chan, Tzu-Hung Lin, Ching-Liou Huang
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Publication number: 20160133594Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.Type: ApplicationFiled: November 7, 2014Publication date: May 12, 2016Inventors: Ching-Liou HUANG, Ta-Jen YU
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Publication number: 20160056105Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer.Type: ApplicationFiled: November 4, 2015Publication date: February 25, 2016Inventors: Kuei-Ti CHAN, Tzu-Hung LIN, Ching-Liou HUANG
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Publication number: 20150357291Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.Type: ApplicationFiled: August 14, 2015Publication date: December 10, 2015Inventors: Tzu-Hung LIN, Ching-Liou HUANG, Thomas Matthew GREGORICH
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Patent number: 9209148Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.Type: GrantFiled: March 20, 2015Date of Patent: December 8, 2015Assignee: MEDIATEK INC.Inventors: Kuei-Ti Chan, Tzu-Hung Lin, Ching-Liou Huang
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Publication number: 20150348932Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Tzu-Hung LIN, Ching-Liou HUANG, Thomas Matthew GREGORICH
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Patent number: 9142526Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.Type: GrantFiled: December 11, 2013Date of Patent: September 22, 2015Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
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Publication number: 20150194403Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.Type: ApplicationFiled: March 20, 2015Publication date: July 9, 2015Inventors: Kuei-Ti CHAN, Tzu-Hung LIN, Ching-Liou HUANG
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Patent number: 8987897Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer.Type: GrantFiled: May 17, 2011Date of Patent: March 24, 2015Assignee: Mediatek Inc.Inventors: Kuei-Ti Chan, Tzu-Hung Lin, Ching-Liou Huang
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Publication number: 20140091481Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.Type: ApplicationFiled: December 11, 2013Publication date: April 3, 2014Applicant: MediaTek Inc.Inventors: Tzu-Hung LIN, Ching-Liou HUANG, Thomas Matthew GREGORICH