Abstract: A flat electrical cable is described. The cable includes a plurality of equally spaced substantially parallel electrical conductors lying in a same plane and extending along the length of the cable. Each conductor has a same diameter D. The cable further includes a common unitary electrically insulating layer encapsulating the plurality of conductors. The insulating layer includes a plurality of cover portions where each cover portion is concentric with a corresponding conductor and has a radial thickness t. t/D is in a range from about 0.50 to about 1.25.

Abstract: A flat electrical cable is described. The cable includes a plurality of equally spaced substantially parallel electrical conductors lying in a same plane and extending along the length of the cable. Each conductor has a same diameter D. The cable further includes a common unitary electrically insulating layer encapsulating the plurality of conductors. The insulating layer includes a plurality of cover portions where each cover portion is concentric with a corresponding conductor and has a radial thickness t. t/D is in a range from about 0.50 to about 1.25.

Abstract: A flat electrical cable is described. The cable includes a plurality of equally spaced substantially parallel electrical conductors lying in a same plane and extending along the length of the cable. Each conductor has a same diameter D. The cable further includes a common unitary electrically insulating layer encapsulating the plurality of conductors. The insulating layer includes a plurality of cover portions where each cover portion is concentric with a corresponding conductor and has a radial thickness t. t/D is in a range from about 0.50 to about 1.25.

Abstract: A method of cleaning post-etch residues on a copper line includes providing a copper line which is divided into a first region and a second region. A dielectric layer is formed on the copper line. After that, the dielectric layer is etched to form openings in the dielectric layer. A number of openings within the first region is more than a number of openings in the second region. During the etching process, a potential difference is formed between the first region and the second region of the copper line. Finally, the dielectric layer and the copper line are cleaned by a solution with a PH value. The PH value has a special relation with the potential difference.

Abstract: A flat electrical cable is described. The cable includes a plurality of equally spaced substantially parallel electrical conductors lying in a same plane and extending along the length of the cable. Each conductor has a same diameter D. The cable further includes a common unitary electrically insulating layer encapsulating the plurality of conductors. The insulating layer includes a plurality of cover portions where each cover portion is concentric with a corresponding conductor and has a radial thickness t. t/D is in a range from about 0.50 to about 1.25.

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a first gate structure, a second gate electrode, a third gate electrode and a protective layer. The first gate structure comprises a first gate electrode disposed on the substrate and a first gate dielectric covering the first gate electrode. The second gate electrode is disposed on and electrically isolated from the first gate electrode. The first gate structure has an extending portion relative to the second gate electrode. The third gate electrode is disposed adjacent to and electrically isolated from the first gate electrode and the second gate electrode. The third gate has an extending portion between a lower surface of the protective layer and an upper surface of the extending portion of the first gate structure.

Abstract: The present disclosure provides a power supply system. The power supply system includes a plurality of power supply devices connected in parallel. Output terminals of the plurality of power supply devices are coupled to a common supply line. Each of the plurality of power supply devices includes a DC-to-DC converter, a transformer, a switching control device, a rectifying device, and a judging device. The judging device receives a feedback voltage, an error signal and a second AC voltage to determine whether the power supply device is normal, wherein the feedback voltage is a voltage division of an output voltage on the common supply line, the error signal is an output of the switching control device, and the second AC voltage is retrieved from a second winding set of the transformer.

Abstract: An electronic fuse apparatus is connected between a power side and a system side. The electronic fuse apparatus mainly includes an electronic fuse, a short-circuit protection switch, a current-sensing module, and a digital control module. The current-sensing module detects an operating current which flows from the power side to the system side. The digital control module generates a control signal to control the electronic fuse. When the current-sensing module detects that the operating current is over-current, the digital control module generates the high-level control signal to turn off the electronic fuse, thus providing an over-current protection. When a short-circuit fault occurs at the system side, the short-circuit protection switch is turned on to turn off the electronic fuse, thus providing a short-circuit protection.

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract: An electronic fuse apparatus is connected between a power side and a system side. The electronic fuse apparatus mainly includes an electronic fuse, a short-circuit protection switch, a current-sensing module, and a digital control module. The current-sensing module detects an operating current which flows from the power side to the system side. The digital control module generates a control signal to control the electronic fuse. When the current-sensing module detects that the operating current is over-current, the digital control module generates the high-level control signal to turn off the electronic fuse, thus providing an over-current protection. When a short-circuit fault occurs at the system side, the short-circuit protection switch is turned on to turn off the electronic fuse, thus providing a short-circuit protection.

Abstract: A circuit layout structure includes a metal interlayer dielectric layer surrounding a metal interconnect and a metal pattern within a scrub line. The scrub line is in the vicinity of the metal interlayer dielectric layer and the metal interconnect. The metal pattern or the metal interconnect are suitably segregated to reduce a capacitance charging effect.

Abstract: The present disclosure provides a power supply system. The power supply system includes a plurality of power supply devices connected in parallel. Output terminals of the plurality of power supply devices are coupled to a common supply line. Each of the plurality of power supply devices includes a DC-to-DC converter, a transformer, a switching control device, a rectifying device, and a judging device. The judging device receives a feedback voltage, an error signal and a second AC voltage to determine whether the power supply device is normal, wherein the feedback voltage is a voltage division of an output voltage on the common supply line, the error signal is an output of the switching control device, and the second AC voltage is retrieved from a second winding set of the transformer.

Abstract: A circuit layout structure includes a metal interlayer dielectric layer surrounding a metal interconnect and a metal pattern within a scrub line. The scrub line is in the vicinity of the metal interlayer dielectric layer and the metal interconnect. The metal pattern or the metal interconnect are suitably segregated to reduce a capacitance charging effect.

Abstract: Antenna shelf tape is disclosed for use with items having radio frequency identification elements or tags associated with items of interest.

Abstract: Techniques are described for protecting components of an RFID tag from electrostatic discharge. For example, an RFID tag includes a conductive cage that shields the components of the RFID tag from electrostatic discharge. The conductive cage includes a first conductive shield on a first side of a substrate of the RFID tag and a second conductive shield on a second side of the substrate. The first conductive shield is positioned on the first side of the substrate to cover an integrated circuit (IC). The second conductive shield is positioned on the second side of the substrate, and is substantially opposite from the first conductive shield. The first and second conductive shields are interconnected by one or more conductors. In this manner, the interconnected conductive shields form a conductive cage that protects the IC from electrostatic discharge.

Abstract: A connector system includes an electrically conductive coupling assembly and a first optical connector assembly. The electrically conductive coupling assembly is configured for mounting in a through-opening in a panel. The first optical connector assembly is configured for engagement with the coupling assembly. The first optical connector assembly includes an electrically conductive connector body that is configured to substantially block a first interconnection opening of the coupling assembly when the first optical connector is engaged with the coupling assembly.

Abstract: A combination tag is disclosed, including a magnetically-responsive element and a radio frequency-responsive element. In one embodiment, the magnetically-responsive element also functions as an antenna for the radio frequency-responsive element.