Patents by Inventor Ching-Lung Tseng

Ching-Lung Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090161280
    Abstract: A thermally protected metal oxide varistor having a pin-type disengaging mechanism includes a varistor body having two metal electrodes coated thereon, an insulating layer enclosing the varistor, a first lead, a second lead, a third lead, a solder, and an elastic member. The first lead and the third lead are coupled to the varistor body. The solder is disposed at an electrical connection point of the varistor body. The elastic member is fixed at an outside of the insulating layer. The second lead includes a connection pin. The connection pin extends through the elastic member and is fixed by the solder to the electrical connection point. When an over-voltage occurs, temperature of the varistor body is raised to melt the solder. A restoring force provided by the elastic member disconnects the second lead from the electrical connection point of the varistor body.
    Type: Application
    Filed: April 8, 2008
    Publication date: June 25, 2009
    Inventor: Ching-Lung Tseng
  • Publication number: 20070217111
    Abstract: A surge varistor contains a varistor member and a disengagement member. The varistor member is parallel-connected to a load; while the disengagement member is series-connected to the load. The disengagement member is an elastic thin plate which contains a base portion and an elastically folded portion. The folded portion is soldered to a contact block extended from a terminal of the varistor member, thereby establishing a series connection between the varistor and disengagement members. When a surge to the load occurs, the varistor member enters shunts a large amount of current. If the temperature rises above a specific threshold, the soldering material binding the folded portion and the contact block is melted and the folded portion escapes from the contact block by its own elasticity, thereby breaking the electrical connection between the varistor and disengagement members.
    Type: Application
    Filed: June 28, 2006
    Publication date: September 20, 2007
    Inventor: Ching-Lung Tseng
  • Publication number: 20050229388
    Abstract: Disclosed is a method for insulating external surfaces of a multi-layer ceramic chip varistor device, wherein a high insulating material is coated on external surfaces of the device before the device's external electrodes are plated in an electroplating process. Then after a heat treatment process, the high insulating material reacts with the device's ceramic body surface material to form an insulating layer. A conventional electroplating process for chip devices can be applied to plate the device's external electrodes with a layer of soldering interface so that the external electrodes have a better solderability. The insulating layer protects the device's ceramic body from being plated and the external electrodes are not short-circuited to cause device failure.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 20, 2005
    Inventors: Sheng-Ming Deng, Ching-Lung Tseng
  • Publication number: 20040124962
    Abstract: An electric device includes a casing made of electric non-conductive material and two circuit members are respectively received in the casing. Two terminals are connected to the two circuit members and extending from an underside of the casing. A metal wire is attached to an outer surface of the casing and two ends of the metal wire extend into the casing and are connected to the two circuit members.
    Type: Application
    Filed: December 26, 2002
    Publication date: July 1, 2004
    Inventor: Ching-Lung Tseng
  • Publication number: 20040119578
    Abstract: A packaging structure includes an upper conductive layer adapted to completely cover an upper area of the electronic element, a first lower conductive layer adapted to cover a left portion of a bottom area of the electronic element, and a second lower conductive layer adapted to cover a right portion of a bottom area of the electronic element. An insulation layer is sandwiched between the first lower conductive layer and the second lower conductive layer. The insulation layer is adapted to cover a central portion of the bottom area of the electronic element.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventor: Ching-Lung Tseng