Patents by Inventor Ching-Ly Yueh
Ching-Ly Yueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960814Abstract: The disclosure provides a wafer searching method and device. The method includes: obtaining a target wafer and a reference wafer; determining a first specific area in the target wafer, and obtaining a first significant distribution feature of the first specific area; determining a second specific area in the reference wafer, and obtaining a second significant distribution feature of the second specific area; in response to determining that the first significant distribution feature corresponds to the second significant distribution feature, estimating a fail pattern similarity between the first specific area and the second specific area; in response to determining that the fail pattern similarity is greater than a threshold, providing the reference wafer as a search result corresponding to the target wafer.Type: GrantFiled: September 1, 2021Date of Patent: April 16, 2024Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Jr-Rung Shiu, Ching-Ly Yueh, Pao-Ju Pao
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Patent number: 11852673Abstract: Provided is a method for generating a chip probing wafer map, and the method includes: obtaining test data associated with a first chip, wherein the first chip includes a plurality of sequentially arranged first dies, and each of the first dies belongs to one of a plurality of bin numbers; assigning different predetermined color codes to the bin numbers; and generating a first general chip probing wafer map for the first chip by assigning a color code of each of the first dies as a corresponding predetermined color code according to the bin number to which each of the first dies belongs.Type: GrantFiled: September 6, 2022Date of Patent: December 26, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Ju Wu, Ching-Ly Yueh
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Publication number: 20220414312Abstract: The disclosure provides a wafer searching method and device. The method includes: obtaining a target wafer and a reference wafer; determining a first specific area in the target wafer, and obtaining a first significant distribution feature of the first specific area; determining a second specific area in the reference wafer, and obtaining a second significant distribution feature of the second specific area; in response to determining that the first significant distribution feature corresponds to the second significant distribution feature, estimating a fail pattern similarity between the first specific area and the second specific area; in response to determining that the fail pattern similarity is greater than a threshold, providing the reference wafer as a search result corresponding to the target wafer.Type: ApplicationFiled: September 1, 2021Publication date: December 29, 2022Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Jr-Rung Shiu, Ching-Ly Yueh, Pao-Ju Pao
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Patent number: 11132790Abstract: The invention provides a wafer map identification method, which includes the following steps: obtaining a wafer map of at least one to-be-identified wafer; performing an image processing operation on the wafer map and a reference pattern, wherein the image processing operation includes: performing a convolution operation on the wafer map and the reference pattern respectively, extracting a critical feature of the wafer map after the convolution operation, and calculating a weight distribution based on the reference pattern after the convolution operation; and calculating a similarity between the processed wafer map and the processed reference pattern to identify the wafer map. The invention also provides a computer-readable recording medium recording the above identification method.Type: GrantFiled: December 20, 2019Date of Patent: September 28, 2021Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Chiu-Chieh Lin, Ching-Ly Yueh
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Publication number: 20210166362Abstract: The invention provides a wafer map identification method, which includes the following steps: obtaining a wafer map of at least one to-be-identified wafer; performing an image processing operation on the wafer map and a reference pattern, wherein the image processing operation includes: performing a convolution operation on the wafer map and the reference pattern respectively, extracting a critical feature of the wafer map after the convolution operation, and calculating a weight distribution based on the reference pattern after the convolution operation; and calculating a similarity between the processed wafer map and the processed reference pattern to identify the wafer map. The invention also provides a computer-readable recording medium recording the above identification method.Type: ApplicationFiled: December 20, 2019Publication date: June 3, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chiu-Chieh Lin, Ching-Ly Yueh
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Publication number: 20180060280Abstract: A nonparametric method for measuring a clustered level of time rank in binary data is provided. A sample set of engineering data is classified into a target group and a reference group, and a rank is set to each sample in a chronological order. A minimum rank and a maximum rank are obtained from the target group, by which a characteristic period is defined. In the characteristic period, an average rank values of the target group and an average rank value of the reference group are calculated. After creating a dummy sample set, the dummy sample set is incorporated into an analysis data set and a new rank is set based on a comparison result of the average rank value of the target group and the average rank value of the reference group, and the minimum rank and the maximum rank of the characteristic period to obtain adjusted test data. A Mann-Whitney U test is executed on the adjusted test data to obtain a clustered level index of time rank in binary data.Type: ApplicationFiled: November 10, 2016Publication date: March 1, 2018Applicant: Powerchip Technology CorporationInventors: Li-Chin Wang, Ching-Ly Yueh, Chien-Chung Chen
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Patent number: 9904660Abstract: A nonparametric method for measuring a clustered level of time rank in binary data is provided. A sample set of engineering data is classified into a target group and a reference group, and a rank is set to each sample in a chronological order. A minimum rank and a maximum rank are obtained from the target group, by which a characteristic period is defined. In the characteristic period, an average rank values of the target group and an average rank value of the reference group are calculated. After creating a dummy sample set, the dummy sample set is incorporated into an analysis data set and a new rank is set based on a comparison result of the average rank value of the target group and the average rank value of the reference group, and the minimum rank and the maximum rank of the characteristic period to obtain adjusted test data. A Mann-Whitney U test is executed on the adjusted test data to obtain a clustered level index of time rank in binary data.Type: GrantFiled: November 10, 2016Date of Patent: February 27, 2018Assignee: Powerchip Technology CorporationInventors: Li-Chin Wang, Ching-Ly Yueh, Chien-Chung Chen
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Patent number: 6968280Abstract: A plurality of lots of wafers, each lot of wafers having a lot number and each wafer of each lot having at least one test parameter generated by performing at least one wafer test item stored in a database, are divided into a high yield group and a low yield group. By analyzing the wafer test parameters of the wafers in the high yield group, a first standard value within a first range is obtained. A first comparison step is then performed to compare each wafer test parameter of each lot in the low yield group with the first standard value and delete lot numbers of lots with wafer test parameters within the first range. Finally, a first amount of residual lots in the low yield group is determined. In response to the first amount of residual lots in the low yield group not equaling to zero, a first searching step is performed to which item of sample test items, in-line QC items and process step items is related to the wafer test item of each residual lot in the low yield group in the database.Type: GrantFiled: March 24, 2003Date of Patent: November 22, 2005Assignee: Powerchip Semiconductor Corp.Inventors: Hung-En Tai, Ching-Ly Yueh
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Publication number: 20040193381Abstract: A plurality of lots of wafers, each lot of wafers having a lot number and each wafer of each lot having at least one test parameter generated by performing at least one wafer test item stored in a database, are divided into a high yield group and a low yield group. By analyzing the wafer test parameters of the wafers in the high yield group, a first standard value within a first range is obtained. A first comparison step is then performed to compare each wafer test parameter of each lot in the low yield group with the first standard value and delete lot numbers of lots with wafer test parameters within the first range. Finally, a first amount of residual lots in the low yield group is determined. In response to the first amount of residual lots in the low yield group not equaling to zero, a first searching step is performed to which item of sample test items, in-line QC items and process step items is related to the wafer test item of each residual lot in the low yield group in the database.Type: ApplicationFiled: March 24, 2003Publication date: September 30, 2004Inventors: Hung-En Tai, Ching-Ly Yueh